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stm32f4xx_hal_rcc.h
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1 /**
2  ******************************************************************************
3  * @file stm32f4xx_hal_rcc.h
4  * @author MCD Application Team
5  * @brief Header file of RCC HAL module.
6  ******************************************************************************
7  * @attention
8  *
9  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10  *
11  * Redistribution and use in source and binary forms, with or without modification,
12  * are permitted provided that the following conditions are met:
13  * 1. Redistributions of source code must retain the above copyright notice,
14  * this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright notice,
16  * this list of conditions and the following disclaimer in the documentation
17  * and/or other materials provided with the distribution.
18  * 3. Neither the name of STMicroelectronics nor the names of its contributors
19  * may be used to endorse or promote products derived from this software
20  * without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  ******************************************************************************
34  */
35 
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_HAL_RCC_H
38 #define __STM32F4xx_HAL_RCC_H
39 
40 #ifdef __cplusplus
41  extern "C" {
42 #endif
43 
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f4xx_hal_def.h"
46 
47 /* Include RCC HAL Extended module */
48 /* (include on top of file since RCC structures are defined in extended file) */
49 #include "stm32f4xx_hal_rcc_ex.h"
50 
51 /** @addtogroup STM32F4xx_HAL_Driver
52  * @{
53  */
54 
55 /** @addtogroup RCC
56  * @{
57  */
58 
59 /* Exported types ------------------------------------------------------------*/
60 /** @defgroup RCC_Exported_Types RCC Exported Types
61  * @{
62  */
63 
64 /**
65  * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
66  */
67 typedef struct
68 {
69  uint32_t OscillatorType; /*!< The oscillators to be configured.
70  This parameter can be a value of @ref RCC_Oscillator_Type */
71 
72  uint32_t HSEState; /*!< The new state of the HSE.
73  This parameter can be a value of @ref RCC_HSE_Config */
74 
75  uint32_t LSEState; /*!< The new state of the LSE.
76  This parameter can be a value of @ref RCC_LSE_Config */
77 
78  uint32_t HSIState; /*!< The new state of the HSI.
79  This parameter can be a value of @ref RCC_HSI_Config */
80 
81  uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
82  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
83 
84  uint32_t LSIState; /*!< The new state of the LSI.
85  This parameter can be a value of @ref RCC_LSI_Config */
86 
87  RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
88 }RCC_OscInitTypeDef;
89 
90 /**
91  * @brief RCC System, AHB and APB busses clock configuration structure definition
92  */
93 typedef struct
94 {
95  uint32_t ClockType; /*!< The clock to be configured.
96  This parameter can be a value of @ref RCC_System_Clock_Type */
97 
98  uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
99  This parameter can be a value of @ref RCC_System_Clock_Source */
100 
101  uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
102  This parameter can be a value of @ref RCC_AHB_Clock_Source */
103 
104  uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
105  This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
106 
107  uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
108  This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
109 
110 }RCC_ClkInitTypeDef;
111 
112 /**
113  * @}
114  */
115 
116 /* Exported constants --------------------------------------------------------*/
117 /** @defgroup RCC_Exported_Constants RCC Exported Constants
118  * @{
119  */
120 
121 /** @defgroup RCC_Oscillator_Type Oscillator Type
122  * @{
123  */
124 #define RCC_OSCILLATORTYPE_NONE 0x00000000U
125 #define RCC_OSCILLATORTYPE_HSE 0x00000001U
126 #define RCC_OSCILLATORTYPE_HSI 0x00000002U
127 #define RCC_OSCILLATORTYPE_LSE 0x00000004U
128 #define RCC_OSCILLATORTYPE_LSI 0x00000008U
129 /**
130  * @}
131  */
132 
133 /** @defgroup RCC_HSE_Config HSE Config
134  * @{
135  */
136 #define RCC_HSE_OFF 0x00000000U
137 #define RCC_HSE_ON RCC_CR_HSEON
138 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
139 /**
140  * @}
141  */
142 
143 /** @defgroup RCC_LSE_Config LSE Config
144  * @{
145  */
146 #define RCC_LSE_OFF 0x00000000U
147 #define RCC_LSE_ON RCC_BDCR_LSEON
148 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
149 /**
150  * @}
151  */
152 
153 /** @defgroup RCC_HSI_Config HSI Config
154  * @{
155  */
156 #define RCC_HSI_OFF ((uint8_t)0x00)
157 #define RCC_HSI_ON ((uint8_t)0x01)
158 
159 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
160 /**
161  * @}
162  */
163 
164 /** @defgroup RCC_LSI_Config LSI Config
165  * @{
166  */
167 #define RCC_LSI_OFF ((uint8_t)0x00)
168 #define RCC_LSI_ON ((uint8_t)0x01)
169 /**
170  * @}
171  */
172 
173 /** @defgroup RCC_PLL_Config PLL Config
174  * @{
175  */
176 #define RCC_PLL_NONE ((uint8_t)0x00)
177 #define RCC_PLL_OFF ((uint8_t)0x01)
178 #define RCC_PLL_ON ((uint8_t)0x02)
179 /**
180  * @}
181  */
182 
183 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
184  * @{
185  */
186 #define RCC_PLLP_DIV2 0x00000002U
187 #define RCC_PLLP_DIV4 0x00000004U
188 #define RCC_PLLP_DIV6 0x00000006U
189 #define RCC_PLLP_DIV8 0x00000008U
190 /**
191  * @}
192  */
193 
194 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
195  * @{
196  */
197 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
198 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
199 /**
200  * @}
201  */
202 
203 /** @defgroup RCC_System_Clock_Type System Clock Type
204  * @{
205  */
206 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U
207 #define RCC_CLOCKTYPE_HCLK 0x00000002U
208 #define RCC_CLOCKTYPE_PCLK1 0x00000004U
209 #define RCC_CLOCKTYPE_PCLK2 0x00000008U
210 /**
211  * @}
212  */
213 
214 /** @defgroup RCC_System_Clock_Source System Clock Source
215  * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
216  * STM32F446xx devices.
217  * @{
218  */
219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
222 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
223 /**
224  * @}
225  */
226 
227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
228  * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
229  * STM32F446xx devices.
230  * @{
231  */
232 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
233 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
234 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
235 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */
236 /**
237  * @}
238  */
239 
240 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
241  * @{
242  */
243 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
244 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
245 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
246 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
247 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
248 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
249 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
250 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
251 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
252 /**
253  * @}
254  */
255 
256 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
257  * @{
258  */
259 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
260 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
261 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
262 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
263 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
264 /**
265  * @}
266  */
267 
268 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
269  * @{
270  */
271 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
272 #define RCC_RTCCLKSOURCE_LSE 0x00000100U
273 #define RCC_RTCCLKSOURCE_LSI 0x00000200U
274 #define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
275 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
276 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
277 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
278 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
279 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
280 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
281 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
282 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
283 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
284 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
285 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
286 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
287 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
288 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
289 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
290 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
291 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
292 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
293 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
294 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
295 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
296 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
297 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
298 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
299 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
300 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
301 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
302 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
303 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
304 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
305 /**
306  * @}
307  */
308 
309 /** @defgroup RCC_MCO_Index MCO Index
310  * @{
311  */
312 #define RCC_MCO1 0x00000000U
313 #define RCC_MCO2 0x00000001U
314 /**
315  * @}
316  */
317 
318 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
319  * @{
320  */
321 #define RCC_MCO1SOURCE_HSI 0x00000000U
322 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
323 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
324 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
325 /**
326  * @}
327  */
328 
329 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
330  * @{
331  */
332 #define RCC_MCODIV_1 0x00000000U
333 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
334 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
335 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
336 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
337 /**
338  * @}
339  */
340 
341 /** @defgroup RCC_Interrupt Interrupts
342  * @{
343  */
344 #define RCC_IT_LSIRDY ((uint8_t)0x01)
345 #define RCC_IT_LSERDY ((uint8_t)0x02)
346 #define RCC_IT_HSIRDY ((uint8_t)0x04)
347 #define RCC_IT_HSERDY ((uint8_t)0x08)
348 #define RCC_IT_PLLRDY ((uint8_t)0x10)
349 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
350 #define RCC_IT_CSS ((uint8_t)0x80)
351 /**
352  * @}
353  */
354 
355 /** @defgroup RCC_Flag Flags
356  * Elements values convention: 0XXYYYYYb
357  * - YYYYY : Flag position in the register
358  * - 0XX : Register index
359  * - 01: CR register
360  * - 10: BDCR register
361  * - 11: CSR register
362  * @{
363  */
364 /* Flags in the CR register */
365 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
366 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
367 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
368 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
369 
370 /* Flags in the BDCR register */
371 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
372 
373 /* Flags in the CSR register */
374 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
375 #define RCC_FLAG_BORRST ((uint8_t)0x79)
376 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
377 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
378 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
379 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
380 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
381 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
382 /**
383  * @}
384  */
385 
386 /**
387  * @}
388  */
389 
390 /* Exported macro ------------------------------------------------------------*/
391 /** @defgroup RCC_Exported_Macros RCC Exported Macros
392  * @{
393  */
394 
395 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
396  * @brief Enable or disable the AHB1 peripheral clock.
397  * @note After reset, the peripheral clock (used for registers read/write access)
398  * is disabled and the application software has to enable this clock before
399  * using it.
400  * @{
401  */
402 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
403  __IO uint32_t tmpreg = 0x00U; \
404  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
405  /* Delay after an RCC peripheral clock enabling */ \
406  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
407  UNUSED(tmpreg); \
408  } while(0U)
409 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
410  __IO uint32_t tmpreg = 0x00U; \
411  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
412  /* Delay after an RCC peripheral clock enabling */ \
413  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
414  UNUSED(tmpreg); \
415  } while(0U)
416 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
417  __IO uint32_t tmpreg = 0x00U; \
418  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
419  /* Delay after an RCC peripheral clock enabling */ \
420  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
421  UNUSED(tmpreg); \
422  } while(0U)
423 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
424  __IO uint32_t tmpreg = 0x00U; \
425  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
426  /* Delay after an RCC peripheral clock enabling */ \
427  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
428  UNUSED(tmpreg); \
429  } while(0U)
430 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
431  __IO uint32_t tmpreg = 0x00U; \
432  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
433  /* Delay after an RCC peripheral clock enabling */ \
434  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
435  UNUSED(tmpreg); \
436  } while(0U)
437 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
438  __IO uint32_t tmpreg = 0x00U; \
439  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
440  /* Delay after an RCC peripheral clock enabling */ \
441  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
442  UNUSED(tmpreg); \
443  } while(0U)
444 
445 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
446 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
447 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
448 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
449 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
450 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
451 /**
452  * @}
453  */
454 
455 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
456  * @brief Get the enable or disable status of the AHB1 peripheral clock.
457  * @note After reset, the peripheral clock (used for registers read/write access)
458  * is disabled and the application software has to enable this clock before
459  * using it.
460  * @{
461  */
462 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
463 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
464 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
465 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
466 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
467 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
468 
469 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
470 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
471 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
472 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
473 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
474 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
475 /**
476  * @}
477  */
478 
479 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
480  * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
481  * @note After reset, the peripheral clock (used for registers read/write access)
482  * is disabled and the application software has to enable this clock before
483  * using it.
484  * @{
485  */
486 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
487  __IO uint32_t tmpreg = 0x00U; \
488  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
489  /* Delay after an RCC peripheral clock enabling */ \
490  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
491  UNUSED(tmpreg); \
492  } while(0U)
493 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
494  __IO uint32_t tmpreg = 0x00U; \
495  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
496  /* Delay after an RCC peripheral clock enabling */ \
497  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
498  UNUSED(tmpreg); \
499  } while(0U)
500 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
501  __IO uint32_t tmpreg = 0x00U; \
502  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
503  /* Delay after an RCC peripheral clock enabling */ \
504  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
505  UNUSED(tmpreg); \
506  } while(0U)
507 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
508  __IO uint32_t tmpreg = 0x00U; \
509  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
510  /* Delay after an RCC peripheral clock enabling */ \
511  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
512  UNUSED(tmpreg); \
513  } while(0U)
514 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
515  __IO uint32_t tmpreg = 0x00U; \
516  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
517  /* Delay after an RCC peripheral clock enabling */ \
518  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
519  UNUSED(tmpreg); \
520  } while(0U)
521 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
522  __IO uint32_t tmpreg = 0x00U; \
523  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
524  /* Delay after an RCC peripheral clock enabling */ \
525  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
526  UNUSED(tmpreg); \
527  } while(0U)
528 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
529  __IO uint32_t tmpreg = 0x00U; \
530  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
531  /* Delay after an RCC peripheral clock enabling */ \
532  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
533  UNUSED(tmpreg); \
534  } while(0U)
535 
536 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
537 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
538 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
539 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
540 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
541 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
542 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
543 /**
544  * @}
545  */
546 
547 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
548  * @brief Get the enable or disable status of the APB1 peripheral clock.
549  * @note After reset, the peripheral clock (used for registers read/write access)
550  * is disabled and the application software has to enable this clock before
551  * using it.
552  * @{
553  */
554 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
555 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
556 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
557 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
558 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
559 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
560 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
561 
562 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
563 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
564 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
565 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
566 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
567 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
568 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
569 /**
570  * @}
571  */
572 
573 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
574  * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
575  * @note After reset, the peripheral clock (used for registers read/write access)
576  * is disabled and the application software has to enable this clock before
577  * using it.
578  * @{
579  */
580 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
581  __IO uint32_t tmpreg = 0x00U; \
582  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
583  /* Delay after an RCC peripheral clock enabling */ \
584  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
585  UNUSED(tmpreg); \
586  } while(0U)
587 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
588  __IO uint32_t tmpreg = 0x00U; \
589  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
590  /* Delay after an RCC peripheral clock enabling */ \
591  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
592  UNUSED(tmpreg); \
593  } while(0U)
594 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
595  __IO uint32_t tmpreg = 0x00U; \
596  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
597  /* Delay after an RCC peripheral clock enabling */ \
598  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
599  UNUSED(tmpreg); \
600  } while(0U)
601 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
602  __IO uint32_t tmpreg = 0x00U; \
603  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
604  /* Delay after an RCC peripheral clock enabling */ \
605  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
606  UNUSED(tmpreg); \
607  } while(0U)
608 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
609  __IO uint32_t tmpreg = 0x00U; \
610  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
611  /* Delay after an RCC peripheral clock enabling */ \
612  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
613  UNUSED(tmpreg); \
614  } while(0U)
615 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
616  __IO uint32_t tmpreg = 0x00U; \
617  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
618  /* Delay after an RCC peripheral clock enabling */ \
619  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
620  UNUSED(tmpreg); \
621  } while(0U)
622 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
623  __IO uint32_t tmpreg = 0x00U; \
624  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
625  /* Delay after an RCC peripheral clock enabling */ \
626  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
627  UNUSED(tmpreg); \
628  } while(0U)
629 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
630  __IO uint32_t tmpreg = 0x00U; \
631  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
632  /* Delay after an RCC peripheral clock enabling */ \
633  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
634  UNUSED(tmpreg); \
635  } while(0U)
636 
637 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
638 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
639 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
640 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
641 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
642 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
643 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
644 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
645 /**
646  * @}
647  */
648 
649 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
650  * @brief Get the enable or disable status of the APB2 peripheral clock.
651  * @note After reset, the peripheral clock (used for registers read/write access)
652  * is disabled and the application software has to enable this clock before
653  * using it.
654  * @{
655  */
656 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
657 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
658 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
659 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
660 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
661 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
662 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
663 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
664 
665 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
666 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
667 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
668 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
669 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
670 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
671 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
672 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
673 /**
674  * @}
675  */
676 
677 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
678  * @brief Force or release AHB1 peripheral reset.
679  * @{
680  */
681 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
682 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
683 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
684 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
685 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
686 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
687 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
688 
689 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
690 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
691 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
692 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
693 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
694 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
695 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
696 /**
697  * @}
698  */
699 
700 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
701  * @brief Force or release APB1 peripheral reset.
702  * @{
703  */
704 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
705 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
706 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
707 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
708 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
709 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
710 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
711 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
712 
713 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
714 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
715 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
716 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
717 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
718 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
719 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
720 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
721 /**
722  * @}
723  */
724 
725 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
726  * @brief Force or release APB2 peripheral reset.
727  * @{
728  */
729 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
730 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
731 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
732 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
733 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
734 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
735 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
736 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
737 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
738 
739 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
740 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
741 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
742 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
743 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
744 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
745 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
746 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
747 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
748 /**
749  * @}
750  */
751 
752 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
753  * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
754  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
755  * power consumption.
756  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
757  * @note By default, all peripheral clocks are enabled during SLEEP mode.
758  * @{
759  */
760 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
761 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
762 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
763 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
764 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
765 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
766 
767 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
768 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
769 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
770 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
771 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
772 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
773 /**
774  * @}
775  */
776 
777 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
778  * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
779  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
780  * power consumption.
781  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
782  * @note By default, all peripheral clocks are enabled during SLEEP mode.
783  * @{
784  */
785 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
786 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
787 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
788 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
789 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
790 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
791 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
792 
793 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
794 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
795 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
796 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
797 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
798 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
799 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
800 /**
801  * @}
802  */
803 
804 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
805  * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
806  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
807  * power consumption.
808  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
809  * @note By default, all peripheral clocks are enabled during SLEEP mode.
810  * @{
811  */
812 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
813 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
814 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
815 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
816 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
817 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
818 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
819 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
820 
821 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
822 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
823 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
824 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
825 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
826 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
827 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
828 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
829 /**
830  * @}
831  */
832 
833 /** @defgroup RCC_HSI_Configuration HSI Configuration
834  * @{
835  */
836 
837 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
838  * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
839  * It is used (enabled by hardware) as system clock source after startup
840  * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
841  * of the HSE used directly or indirectly as system clock (if the Clock
842  * Security System CSS is enabled).
843  * @note HSI can not be stopped if it is used as system clock source. In this case,
844  * you have to select another source of the system clock then stop the HSI.
845  * @note After enabling the HSI, the application software should wait on HSIRDY
846  * flag to be set indicating that HSI clock is stable and can be used as
847  * system clock source.
848  * This parameter can be: ENABLE or DISABLE.
849  * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
850  * clock cycles.
851  */
852 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
853 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
854 
855 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
856  * @note The calibration is used to compensate for the variations in voltage
857  * and temperature that influence the frequency of the internal HSI RC.
858  * @param __HSICalibrationValue__ specifies the calibration trimming value.
859  * (default is RCC_HSICALIBRATION_DEFAULT).
860  * This parameter must be a number between 0 and 0x1F.
861  */
862 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
863  RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
864 /**
865  * @}
866  */
867 
868 /** @defgroup RCC_LSI_Configuration LSI Configuration
869  * @{
870  */
871 
872 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
873  * @note After enabling the LSI, the application software should wait on
874  * LSIRDY flag to be set indicating that LSI clock is stable and can
875  * be used to clock the IWDG and/or the RTC.
876  * @note LSI can not be disabled if the IWDG is running.
877  * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
878  * clock cycles.
879  */
880 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
881 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
882 /**
883  * @}
884  */
885 
886 /** @defgroup RCC_HSE_Configuration HSE Configuration
887  * @{
888  */
889 
890 /**
891  * @brief Macro to configure the External High Speed oscillator (HSE).
892  * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
893  * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
894  * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
895  * software should wait on HSERDY flag to be set indicating that HSE clock
896  * is stable and can be used to clock the PLL and/or system clock.
897  * @note HSE state can not be changed if it is used directly or through the
898  * PLL as system clock. In this case, you have to select another source
899  * of the system clock then change the HSE state (ex. disable it).
900  * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
901  * @note This function reset the CSSON bit, so if the clock security system(CSS)
902  * was previously enabled you have to enable it again after calling this
903  * function.
904  * @param __STATE__ specifies the new state of the HSE.
905  * This parameter can be one of the following values:
906  * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
907  * 6 HSE oscillator clock cycles.
908  * @arg RCC_HSE_ON: turn ON the HSE oscillator.
909  * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
910  */
911 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
912  do { \
913  if ((__STATE__) == RCC_HSE_ON) \
914  { \
915  SET_BIT(RCC->CR, RCC_CR_HSEON); \
916  } \
917  else if ((__STATE__) == RCC_HSE_BYPASS) \
918  { \
919  SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
920  SET_BIT(RCC->CR, RCC_CR_HSEON); \
921  } \
922  else \
923  { \
924  CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
925  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
926  } \
927  } while(0U)
928 /**
929  * @}
930  */
931 
932 /** @defgroup RCC_LSE_Configuration LSE Configuration
933  * @{
934  */
935 
936 /**
937  * @brief Macro to configure the External Low Speed oscillator (LSE).
938  * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
939  * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
940  * @note As the LSE is in the Backup domain and write access is denied to
941  * this domain after reset, you have to enable write access using
942  * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
943  * (to be done once after reset).
944  * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
945  * software should wait on LSERDY flag to be set indicating that LSE clock
946  * is stable and can be used to clock the RTC.
947  * @param __STATE__ specifies the new state of the LSE.
948  * This parameter can be one of the following values:
949  * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
950  * 6 LSE oscillator clock cycles.
951  * @arg RCC_LSE_ON: turn ON the LSE oscillator.
952  * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
953  */
954 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
955  do { \
956  if((__STATE__) == RCC_LSE_ON) \
957  { \
958  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
959  } \
960  else if((__STATE__) == RCC_LSE_BYPASS) \
961  { \
962  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
963  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
964  } \
965  else \
966  { \
967  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
968  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
969  } \
970  } while(0U)
971 /**
972  * @}
973  */
974 
975 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
976  * @{
977  */
978 
979 /** @brief Macros to enable or disable the RTC clock.
980  * @note These macros must be used only after the RTC clock source was selected.
981  */
982 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
983 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
984 
985 /** @brief Macros to configure the RTC clock (RTCCLK).
986  * @note As the RTC clock configuration bits are in the Backup domain and write
987  * access is denied to this domain after reset, you have to enable write
988  * access using the Power Backup Access macro before to configure
989  * the RTC clock source (to be done once after reset).
990  * @note Once the RTC clock is configured it can't be changed unless the
991  * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
992  * a Power On Reset (POR).
993  * @param __RTCCLKSource__ specifies the RTC clock source.
994  * This parameter can be one of the following values:
995  @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
996  * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
997  * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
998  * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
999  * as RTC clock, where x:[2,31]
1000  * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
1001  * work in STOP and STANDBY modes, and can be used as wake-up source.
1002  * However, when the HSE clock is used as RTC clock source, the RTC
1003  * cannot be used in STOP and STANDBY modes.
1004  * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
1005  * RTC clock source).
1006  */
1007 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
1008  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
1009 
1010 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
1011  RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
1012  } while(0U)
1013 
1014 /** @brief Macro to get the RTC clock source.
1015  * @retval The clock source can be one of the following values:
1016  * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
1017  * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
1018  * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
1019  * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
1020  */
1021 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
1022 
1023 /**
1024  * @brief Get the RTC and HSE clock divider (RTCPRE).
1025  * @retval Returned value can be one of the following values:
1026  * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
1027  * as RTC clock, where x:[2,31]
1028  */
1029 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
1030 
1031 /** @brief Macros to force or release the Backup domain reset.
1032  * @note This function resets the RTC peripheral (including the backup registers)
1033  * and the RTC clock source selection in RCC_CSR register.
1034  * @note The BKPSRAM is not affected by this reset.
1035  */
1036 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
1037 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
1038 /**
1039  * @}
1040  */
1041 
1042 /** @defgroup RCC_PLL_Configuration PLL Configuration
1043  * @{
1044  */
1045 
1046 /** @brief Macros to enable or disable the main PLL.
1047  * @note After enabling the main PLL, the application software should wait on
1048  * PLLRDY flag to be set indicating that PLL clock is stable and can
1049  * be used as system clock source.
1050  * @note The main PLL can not be disabled if it is used as system clock source
1051  * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
1052  */
1053 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
1054 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
1055 
1056 /** @brief Macro to configure the PLL clock source.
1057  * @note This function must be used only when the main PLL is disabled.
1058  * @param __PLLSOURCE__ specifies the PLL entry clock source.
1059  * This parameter can be one of the following values:
1060  * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
1061  * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
1062  *
1063  */
1064 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
1065 
1066 /** @brief Macro to configure the PLL multiplication factor.
1067  * @note This function must be used only when the main PLL is disabled.
1068  * @param __PLLM__ specifies the division factor for PLL VCO input clock
1069  * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
1070  * @note You have to set the PLLM parameter correctly to ensure that the VCO input
1071  * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
1072  * of 2 MHz to limit PLL jitter.
1073  *
1074  */
1075 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
1076 /**
1077  * @}
1078  */
1079 
1080 /** @defgroup RCC_Get_Clock_source Get Clock source
1081  * @{
1082  */
1083 /**
1084  * @brief Macro to configure the system clock source.
1085  * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
1086  * This parameter can be one of the following values:
1087  * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
1088  * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
1089  * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
1090  * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
1091  * parameter is available only for STM32F446xx devices.
1092  */
1093 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
1094 
1095 /** @brief Macro to get the clock source used as system clock.
1096  * @retval The clock source used as system clock. The returned value can be one
1097  * of the following:
1098  * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
1099  * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
1100  * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
1101  * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
1102  * is available only for STM32F446xx devices.
1103  */
1104 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
1105 
1106 /** @brief Macro to get the oscillator used as PLL clock source.
1107  * @retval The oscillator used as PLL clock source. The returned value can be one
1108  * of the following:
1109  * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
1110  * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
1111  */
1112 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
1113 /**
1114  * @}
1115  */
1116 
1117 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
1118  * @{
1119  */
1120 
1121 /** @brief Macro to configure the MCO1 clock.
1122  * @param __MCOCLKSOURCE__ specifies the MCO clock source.
1123  * This parameter can be one of the following values:
1124  * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
1125  * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
1126  * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
1127  * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
1128  * @param __MCODIV__ specifies the MCO clock prescaler.
1129  * This parameter can be one of the following values:
1130  * @arg RCC_MCODIV_1: no division applied to MCOx clock
1131  * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
1132  * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
1133  * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
1134  * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
1135  */
1136 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1137  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1138 
1139 /** @brief Macro to configure the MCO2 clock.
1140  * @param __MCOCLKSOURCE__ specifies the MCO clock source.
1141  * This parameter can be one of the following values:
1142  * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
1143  * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
1144  * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
1145  * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
1146  * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
1147  * @param __MCODIV__ specifies the MCO clock prescaler.
1148  * This parameter can be one of the following values:
1149  * @arg RCC_MCODIV_1: no division applied to MCOx clock
1150  * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
1151  * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
1152  * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
1153  * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
1154  * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
1155  * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
1156  */
1157 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1158  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
1159 /**
1160  * @}
1161  */
1162 
1163 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
1164  * @brief macros to manage the specified RCC Flags and interrupts.
1165  * @{
1166  */
1167 
1168 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
1169  * the selected interrupts).
1170  * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
1171  * This parameter can be any combination of the following values:
1172  * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1173  * @arg RCC_IT_LSERDY: LSE ready interrupt.
1174  * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1175  * @arg RCC_IT_HSERDY: HSE ready interrupt.
1176  * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1177  * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1178  */
1179 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1180 
1181 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
1182  * the selected interrupts).
1183  * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
1184  * This parameter can be any combination of the following values:
1185  * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1186  * @arg RCC_IT_LSERDY: LSE ready interrupt.
1187  * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1188  * @arg RCC_IT_HSERDY: HSE ready interrupt.
1189  * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1190  * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1191  */
1192 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1193 
1194 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
1195  * bits to clear the selected interrupt pending bits.
1196  * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
1197  * This parameter can be any combination of the following values:
1198  * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1199  * @arg RCC_IT_LSERDY: LSE ready interrupt.
1200  * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1201  * @arg RCC_IT_HSERDY: HSE ready interrupt.
1202  * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1203  * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1204  * @arg RCC_IT_CSS: Clock Security System interrupt
1205  */
1206 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1207 
1208 /** @brief Check the RCC's interrupt has occurred or not.
1209  * @param __INTERRUPT__ specifies the RCC interrupt source to check.
1210  * This parameter can be one of the following values:
1211  * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1212  * @arg RCC_IT_LSERDY: LSE ready interrupt.
1213  * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1214  * @arg RCC_IT_HSERDY: HSE ready interrupt.
1215  * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1216  * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1217  * @arg RCC_IT_CSS: Clock Security System interrupt
1218  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1219  */
1220 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1221 
1222 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
1223  * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
1224  */
1225 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1226 
1227 /** @brief Check RCC flag is set or not.
1228  * @param __FLAG__ specifies the flag to check.
1229  * This parameter can be one of the following values:
1230  * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
1231  * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
1232  * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
1233  * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
1234  * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
1235  * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
1236  * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
1237  * @arg RCC_FLAG_PINRST: Pin reset.
1238  * @arg RCC_FLAG_PORRST: POR/PDR reset.
1239  * @arg RCC_FLAG_SFTRST: Software reset.
1240  * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
1241  * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
1242  * @arg RCC_FLAG_LPWRRST: Low Power reset.
1243  * @retval The new state of __FLAG__ (TRUE or FALSE).
1244  */
1245 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
1246 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
1247 
1248 /**
1249  * @}
1250  */
1251 
1252 /**
1253  * @}
1254  */
1255 
1256 /* Exported functions --------------------------------------------------------*/
1257  /** @addtogroup RCC_Exported_Functions
1258  * @{
1259  */
1260 
1261 /** @addtogroup RCC_Exported_Functions_Group1
1262  * @{
1263  */
1264 /* Initialization and de-initialization functions ******************************/
1265 HAL_StatusTypeDef HAL_RCC_DeInit(void);
1266 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1267 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1268 /**
1269  * @}
1270  */
1271 
1272 /** @addtogroup RCC_Exported_Functions_Group2
1273  * @{
1274  */
1275 /* Peripheral Control functions ************************************************/
1276 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1277 void HAL_RCC_EnableCSS(void);
1278 void HAL_RCC_DisableCSS(void);
1279 uint32_t HAL_RCC_GetSysClockFreq(void);
1280 uint32_t HAL_RCC_GetHCLKFreq(void);
1281 uint32_t HAL_RCC_GetPCLK1Freq(void);
1282 uint32_t HAL_RCC_GetPCLK2Freq(void);
1283 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1284 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1285 
1286 /* CSS NMI IRQ handler */
1287 void HAL_RCC_NMI_IRQHandler(void);
1288 
1289 /* User Callbacks in non blocking mode (IT mode) */
1290 void HAL_RCC_CSSCallback(void);
1291 
1292 /**
1293  * @}
1294  */
1295 
1296 /**
1297  * @}
1298  */
1299 
1300 /* Private types -------------------------------------------------------------*/
1301 /* Private variables ---------------------------------------------------------*/
1302 /* Private constants ---------------------------------------------------------*/
1303 /** @defgroup RCC_Private_Constants RCC Private Constants
1304  * @{
1305  */
1306 
1307 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
1308  * @brief RCC registers bit address in the alias region
1309  * @{
1310  */
1311 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
1312 /* --- CR Register --- */
1313 /* Alias word address of HSION bit */
1314 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
1315 #define RCC_HSION_BIT_NUMBER 0x00U
1316 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
1317 /* Alias word address of CSSON bit */
1318 #define RCC_CSSON_BIT_NUMBER 0x13U
1319 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
1320 /* Alias word address of PLLON bit */
1321 #define RCC_PLLON_BIT_NUMBER 0x18U
1322 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
1323 
1324 /* --- BDCR Register --- */
1325 /* Alias word address of RTCEN bit */
1326 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
1327 #define RCC_RTCEN_BIT_NUMBER 0x0FU
1328 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
1329 /* Alias word address of BDRST bit */
1330 #define RCC_BDRST_BIT_NUMBER 0x10U
1331 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
1332 
1333 /* --- CSR Register --- */
1334 /* Alias word address of LSION bit */
1335 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
1336 #define RCC_LSION_BIT_NUMBER 0x00U
1337 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
1338 
1339 /* CR register byte 3 (Bits[23:16]) base address */
1340 #define RCC_CR_BYTE2_ADDRESS 0x40023802U
1341 
1342 /* CIR register byte 2 (Bits[15:8]) base address */
1343 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
1344 
1345 /* CIR register byte 3 (Bits[23:16]) base address */
1346 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
1347 
1348 /* BDCR register base address */
1349 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
1350 
1351 #define RCC_DBP_TIMEOUT_VALUE 2U
1352 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1353 
1354 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1355 #define HSI_TIMEOUT_VALUE 2U /* 2 ms */
1356 #define LSI_TIMEOUT_VALUE 2U /* 2 ms */
1357 #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
1358 
1359 /**
1360  * @}
1361  */
1362 
1363 /**
1364  * @}
1365  */
1366 
1367 /* Private macros ------------------------------------------------------------*/
1368 /** @defgroup RCC_Private_Macros RCC Private Macros
1369  * @{
1370  */
1371 
1372 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
1373  * @{
1374  */
1375 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
1376 
1377 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
1378  ((HSE) == RCC_HSE_BYPASS))
1379 
1380 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
1381  ((LSE) == RCC_LSE_BYPASS))
1382 
1383 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
1384 
1385 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
1386 
1387 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
1388 
1389 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
1390  ((SOURCE) == RCC_PLLSOURCE_HSE))
1391 
1392 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
1393  ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
1394  ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
1395  ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
1396 
1397 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
1398  ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
1399  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
1400  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
1401  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
1402  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
1403  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
1404  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
1405  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
1406  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
1407  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
1408  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
1409  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
1410  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
1411  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
1412  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
1413  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
1414  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
1415  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
1416  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
1417  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
1418  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
1419  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
1420  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
1421  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
1422  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
1423  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
1424  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
1425  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
1426  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
1427  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
1428  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
1429 
1430 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
1431 
1432 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
1433 
1434 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
1435 
1436 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
1437  ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
1438  ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
1439  ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
1440  ((HCLK) == RCC_SYSCLK_DIV512))
1441 
1442 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
1443 
1444 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
1445  ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
1446  ((PCLK) == RCC_HCLK_DIV16))
1447 
1448 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
1449 
1450 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
1451  ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
1452 
1453 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
1454  ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
1455  ((DIV) == RCC_MCODIV_5))
1456 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
1457 
1458 /**
1459  * @}
1460  */
1461 
1462 /**
1463  * @}
1464  */
1465 
1466 /**
1467  * @}
1468  */
1469 
1470 /**
1471  * @}
1472  */
1473 
1474 #ifdef __cplusplus
1475 }
1476 #endif
1477 
1478 #endif /* __STM32F4xx_HAL_RCC_H */
1479 
1480 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
stm32f4xx_hal_rcc_ex.h
Header file of RCC HAL Extension module.
HAL_RCC_GetHCLKFreq
uint32_t HAL_RCC_GetHCLKFreq(void)
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition: stm32f4xx_hal_rcc.h:93
HAL_RCC_OscConfig
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_ClkInitTypeDef::SYSCLKSource
uint32_t SYSCLKSource
Definition: stm32f4xx_hal_rcc.h:98
HAL_RCC_DeInit
HAL_StatusTypeDef HAL_RCC_DeInit(void)
RCC_OscInitTypeDef::LSEState
uint32_t LSEState
Definition: stm32f4xx_hal_rcc.h:75
HAL_RCC_NMI_IRQHandler
void HAL_RCC_NMI_IRQHandler(void)
HAL_RCC_DisableCSS
void HAL_RCC_DisableCSS(void)
RCC_OscInitTypeDef::OscillatorType
uint32_t OscillatorType
Definition: stm32f4xx_hal_rcc.h:69
HAL_RCC_MCOConfig
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
RCC_OscInitTypeDef::HSEState
uint32_t HSEState
Definition: stm32f4xx_hal_rcc.h:72
HAL_RCC_GetPCLK2Freq
uint32_t HAL_RCC_GetPCLK2Freq(void)
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:55
HAL_RCC_CSSCallback
void HAL_RCC_CSSCallback(void)
RCC_OscInitTypeDef::HSIState
uint32_t HSIState
Definition: stm32f4xx_hal_rcc.h:78
HAL_RCC_EnableCSS
void HAL_RCC_EnableCSS(void)
RCC_OscInitTypeDef::PLL
RCC_PLLInitTypeDef PLL
Definition: stm32f4xx_hal_rcc.h:87
RCC_ClkInitTypeDef::APB1CLKDivider
uint32_t APB1CLKDivider
Definition: stm32f4xx_hal_rcc.h:104
HAL_RCC_GetOscConfig
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitTypeDef::HSICalibrationValue
uint32_t HSICalibrationValue
Definition: stm32f4xx_hal_rcc.h:81
RCC_ClkInitTypeDef::AHBCLKDivider
uint32_t AHBCLKDivider
Definition: stm32f4xx_hal_rcc.h:101
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
RCC_OscInitTypeDef::LSIState
uint32_t LSIState
Definition: stm32f4xx_hal_rcc.h:84
RCC_ClkInitTypeDef::ClockType
uint32_t ClockType
Definition: stm32f4xx_hal_rcc.h:95
HAL_RCC_ClockConfig
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
RCC_ClkInitTypeDef::APB2CLKDivider
uint32_t APB2CLKDivider
Definition: stm32f4xx_hal_rcc.h:107
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.
Definition: stm32f4xx_hal_rcc.h:67
HAL_RCC_GetClockConfig
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition: stm32f4xx_hal_rcc_ex.h:63