APB2 Peripheral Clock Enable Disable

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Collaboration diagram for APB2 Peripheral Clock Enable Disable:

Macros
#define	__HAL_RCC_TIM1_CLK_ENABLE()
#define	__HAL_RCC_USART1_CLK_ENABLE()
#define	__HAL_RCC_USART6_CLK_ENABLE()
#define	__HAL_RCC_ADC1_CLK_ENABLE()
#define	__HAL_RCC_SPI1_CLK_ENABLE()
#define	__HAL_RCC_SYSCFG_CLK_ENABLE()
#define	__HAL_RCC_TIM9_CLK_ENABLE()
#define	__HAL_RCC_TIM11_CLK_ENABLE()
#define	__HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define	__HAL_RCC_USART1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
#define	__HAL_RCC_USART6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
#define	__HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
#define	__HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define	__HAL_RCC_SYSCFG_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
#define	__HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
#define	__HAL_RCC_TIM11_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

__HAL_RCC_TIM1_CLK_ENABLE

#define __HAL_RCC_TIM1_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_USART1_CLK_ENABLE

#define __HAL_RCC_USART1_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_USART6_CLK_ENABLE

#define __HAL_RCC_USART6_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_ADC1_CLK_ENABLE

#define __HAL_RCC_ADC1_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_SPI1_CLK_ENABLE

#define __HAL_RCC_SPI1_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_SYSCFG_CLK_ENABLE

#define __HAL_RCC_SYSCFG_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_TIM9_CLK_ENABLE

#define __HAL_RCC_TIM9_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_TIM11_CLK_ENABLE

#define __HAL_RCC_TIM11_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_TIM1_CLK_DISABLE

#define __HAL_RCC_TIM1_CLK_DISABLE

(

)

(RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

__HAL_RCC_USART1_CLK_DISABLE

#define __HAL_RCC_USART1_CLK_DISABLE

(

)

(RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

__HAL_RCC_USART6_CLK_DISABLE

#define __HAL_RCC_USART6_CLK_DISABLE

(

)

(RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))

__HAL_RCC_ADC1_CLK_DISABLE

#define __HAL_RCC_ADC1_CLK_DISABLE

(

)

(RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

__HAL_RCC_SPI1_CLK_DISABLE

#define __HAL_RCC_SPI1_CLK_DISABLE

(

)

(RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

__HAL_RCC_SYSCFG_CLK_DISABLE

#define __HAL_RCC_SYSCFG_CLK_DISABLE

(

)

(RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

__HAL_RCC_TIM9_CLK_DISABLE

#define __HAL_RCC_TIM9_CLK_DISABLE

(

)

(RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))

__HAL_RCC_TIM11_CLK_DISABLE

#define __HAL_RCC_TIM11_CLK_DISABLE

(

)

(RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))