APB1 Peripheral Clock Enable Disable

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Collaboration diagram for APB1 Peripheral Clock Enable Disable:

Macros
#define	__HAL_RCC_TIM5_CLK_ENABLE()
#define	__HAL_RCC_WWDG_CLK_ENABLE()
#define	__HAL_RCC_SPI2_CLK_ENABLE()
#define	__HAL_RCC_USART2_CLK_ENABLE()
#define	__HAL_RCC_I2C1_CLK_ENABLE()
#define	__HAL_RCC_I2C2_CLK_ENABLE()
#define	__HAL_RCC_PWR_CLK_ENABLE()
#define	__HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define	__HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define	__HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define	__HAL_RCC_USART2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define	__HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define	__HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define	__HAL_RCC_PWR_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

__HAL_RCC_TIM5_CLK_ENABLE

#define __HAL_RCC_TIM5_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_WWDG_CLK_ENABLE

#define __HAL_RCC_WWDG_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_SPI2_CLK_ENABLE

#define __HAL_RCC_SPI2_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_USART2_CLK_ENABLE

#define __HAL_RCC_USART2_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_I2C1_CLK_ENABLE

#define __HAL_RCC_I2C1_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_I2C2_CLK_ENABLE

#define __HAL_RCC_I2C2_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_PWR_CLK_ENABLE

#define __HAL_RCC_PWR_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

__HAL_RCC_TIM5_CLK_DISABLE

#define __HAL_RCC_TIM5_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

__HAL_RCC_WWDG_CLK_DISABLE

#define __HAL_RCC_WWDG_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

__HAL_RCC_SPI2_CLK_DISABLE

#define __HAL_RCC_SPI2_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

__HAL_RCC_USART2_CLK_DISABLE

#define __HAL_RCC_USART2_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

__HAL_RCC_I2C1_CLK_DISABLE

#define __HAL_RCC_I2C1_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

__HAL_RCC_I2C2_CLK_DISABLE

#define __HAL_RCC_I2C2_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

__HAL_RCC_PWR_CLK_DISABLE

#define __HAL_RCC_PWR_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))