Prusa MINI Firmware overview
sys.h File Reference
#include "stdint.h"
#include "shared_config.h"

Go to the source code of this file.

Functions

void sys_reset (void)
 
void sys_dfu_boot (void)
 
int sys_pll_is_enabled (void)
 
void sys_pll_disable (void)
 
void sys_pll_enable (void)
 
int sys_sscg_is_enabled (void)
 
void sys_sscg_disable (void)
 
void sys_sscg_enable (void)
 
void sys_sscg_set_config (int freq, int depth)
 
int sys_sscg_get_config (float *pfreq, float *pdepth)
 
void sys_spi_set_prescaler (int prescaler_num)
 
int sys_fw_update_is_enabled (void)
 
void sys_fw_update_enable (void)
 
void sys_fw_update_disable (void)
 
int sys_fw_update_on_restart_is_enabled (void)
 
void sys_fw_update_on_restart_enable (void)
 
void sys_fw_update_on_restart_disable (void)
 
int sys_fw_is_valid (void)
 
int sys_fw_invalidate (void)
 
int sys_fw_validate (void)
 
int sys_flash_is_empty (void *ptr, int size)
 
int sys_flash_write (void *dst, void *src, int size)
 
int sys_flash_erase_sector (unsigned int sector)
 

Variables

volatile data_exchange_t ram_data_exchange
 

Function Documentation

◆ sys_reset()

void sys_reset ( void  )
20  {
21  uint32_t aircr = SCB->AIRCR & 0x0000ffff; //read AIRCR, mask VECTKEY
22  if (__get_PRIMASK() & 1)
23  __disable_irq(); //disable irq if enabled
24  aircr |= 0x05fa0000; //set VECTKEY
25  aircr |= 0x00000004; //set SYSRESETREQ
26  SCB->AIRCR = aircr; //write AIRCR
27  while (1)
28  ; //endless loop
29 }
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◆ sys_dfu_boot()

void sys_dfu_boot ( void  )
31  {
32 }
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◆ sys_pll_is_enabled()

int sys_pll_is_enabled ( void  )
48  {
49  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
50  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
51  uint32_t FLatency;
52  HAL_RCC_GetOscConfig(&RCC_OscInitStruct); //read Osc config
53  HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &FLatency); //read Clk config
54  return ((RCC_OscInitStruct.PLL.PLLState == RCC_PLL_ON) && (RCC_ClkInitStruct.SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)) ? 1 : 0;
55 }
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◆ sys_pll_disable()

void sys_pll_disable ( void  )
57  {
58  int irq = __get_PRIMASK() & 1;
59  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
60  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
61  uint32_t FLatency;
62  HAL_RCC_GetOscConfig(&RCC_OscInitStruct); //read Osc config
63  HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &FLatency); //read Clk config
64  if ((RCC_OscInitStruct.PLL.PLLState == RCC_PLL_OFF) && (RCC_ClkInitStruct.SYSCLKSource != RCC_SYSCLKSOURCE_PLLCLK))
65  return; //already disabled - exit
66  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF; //set PLL off
67  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; //set CLK source HSE
68  if (irq)
69  __disable_irq(); //disable irq while switching clock
70  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, sys_calc_flash_latency(HSE_VALUE)); //set Clk config first
71  HAL_RCC_OscConfig(&RCC_OscInitStruct); //set Osc config
72  if (irq)
73  __enable_irq();
74  //HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
75  //HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &FLatency);
76 }
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◆ sys_pll_enable()

void sys_pll_enable ( void  )
78  {
79  int irq = __get_PRIMASK() & 1;
80  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
81  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
82 
83  /*
84  RCC_OscInitTypeDef RCC_OscInitStruct1 = {0};
85  RCC_ClkInitTypeDef RCC_ClkInitStruct1 = {0};
86 
87  RCC_OscInitStruct1.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
88  RCC_OscInitStruct1.HSEState = RCC_HSE_ON;
89  RCC_OscInitStruct1.LSIState = RCC_LSI_ON;
90  RCC_OscInitStruct1.PLL.PLLState = RCC_PLL_ON;
91  RCC_OscInitStruct1.PLL.PLLSource = RCC_PLLSOURCE_HSE;
92  RCC_OscInitStruct1.PLL.PLLM = 6;
93  RCC_OscInitStruct1.PLL.PLLN = 100;
94  RCC_OscInitStruct1.PLL.PLLP = RCC_PLLP_DIV2;
95  RCC_OscInitStruct1.PLL.PLLQ = 7;
96  RCC_ClkInitStruct1.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
97  |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
98  RCC_ClkInitStruct1.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
99  RCC_ClkInitStruct1.AHBCLKDivider = RCC_SYSCLK_DIV1;
100  RCC_ClkInitStruct1.APB1CLKDivider = RCC_HCLK_DIV4;
101  RCC_ClkInitStruct1.APB2CLKDivider = RCC_HCLK_DIV2;
102 */
103 
104  uint32_t FLatency;
105  HAL_RCC_GetOscConfig(&RCC_OscInitStruct); //read Osc config
106  HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &FLatency); //read Clk config
107  if ((RCC_OscInitStruct.PLL.PLLState == RCC_PLL_ON) && (RCC_ClkInitStruct.SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK))
108  return; //already enabled - exit
109  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; //set PLL off
110  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; //set CLK source HSE
111  if (irq)
112  __disable_irq(); //disable irq while switching clock
113  HAL_RCC_OscConfig(&RCC_OscInitStruct); //set Osc config first
114  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, sys_calc_flash_latency(sys_pll_freq)); //set Clk config
115  if (irq)
116  __enable_irq();
117  //HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
118  //HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &FLatency);
119 }
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◆ sys_sscg_is_enabled()

int sys_sscg_is_enabled ( void  )
121  {
122  return (RCC->SSCGR & RCC_SSCGR_SSCGEN_Msk) ? 1 : 0;
123 }
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◆ sys_sscg_disable()

void sys_sscg_disable ( void  )
125  {
126  uint32_t sscgr = RCC->SSCGR;
127  __disable_irq();
128  if ((sscgr & RCC_SSCGR_SSCGEN_Msk) == 0)
129  return;
130  sscgr &= ~((1 << RCC_SSCGR_SSCGEN_Pos) & RCC_SSCGR_SSCGEN_Msk);
131  sys_pll_disable();
132  RCC->SSCGR = sscgr;
133  sys_pll_enable();
134  _dbg0("written SSCGR = 0x%08lx (%lu)", sscgr, sscgr);
135  sscgr = RCC->SSCGR;
136  _dbg0("readback SSCGR = 0x%08lx (%lu)", sscgr, sscgr);
137  __enable_irq();
138 }
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◆ sys_sscg_enable()

void sys_sscg_enable ( void  )
140  {
141  uint32_t sscgr = RCC->SSCGR;
142  uint32_t modper = ((sscgr & RCC_SSCGR_MODPER_Msk) >> RCC_SSCGR_MODPER_Pos);
143  uint32_t incstep = ((sscgr & RCC_SSCGR_INCSTEP_Msk) >> RCC_SSCGR_INCSTEP_Pos);
144  if (modper == 0)
145  return;
146  if (incstep == 0)
147  return;
148  sscgr |= (1 << RCC_SSCGR_SSCGEN_Pos) & RCC_SSCGR_SSCGEN_Msk;
149  __disable_irq();
150  sys_pll_disable();
151  RCC->SSCGR = sscgr;
152  sys_pll_enable();
153  _dbg0("written SSCGR = 0x%08lx (%lu)", sscgr, sscgr);
154  sscgr = RCC->SSCGR;
155  _dbg0("readback SSCGR = 0x%08lx (%lu)", sscgr, sscgr);
156  __enable_irq();
157 }
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◆ sys_sscg_set_config()

void sys_sscg_set_config ( int  freq,
int  depth 
)
159  {
160  int fpll = 2000000; //input pll frequency = 2MHz
161  int plln;
162  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
163  uint32_t sscgr = RCC->SSCGR; //read current state of sscg
164  uint32_t modper = ((sscgr & RCC_SSCGR_MODPER_Msk) >> RCC_SSCGR_MODPER_Pos);
165  uint32_t incstep = ((sscgr & RCC_SSCGR_INCSTEP_Msk) >> RCC_SSCGR_INCSTEP_Pos);
166  uint32_t spreadsel = ((sscgr & RCC_SSCGR_SPREADSEL_Msk) >> RCC_SSCGR_SPREADSEL_Pos);
167  uint32_t sscgen = ((sscgr & RCC_SSCGR_SSCGEN_Msk) >> RCC_SSCGR_SSCGEN_Pos);
168  _dbg0("SSCGR = 0x%08lx (%lu)", sscgr, sscgr);
169  _dbg0(" MODPER = 0x%08lx (%lu)", modper, modper);
170  _dbg0(" INCSTEP = 0x%08lx (%lu)", incstep, incstep);
171  _dbg0(" SPREADSEL = 0x%08lx (%lu)", spreadsel, spreadsel);
172  _dbg0(" SSCGEN = 0x%08lx (%lu)", sscgen, sscgen);
173  HAL_RCC_GetOscConfig(&RCC_OscInitStruct); //read Osc config
174  plln = RCC_OscInitStruct.PLL.PLLN;
175  //modulation frequency = freq
176  //MODPER = round [fPLL_IN / (4 x fMOD)]
177  modper = (uint32_t)(((float)fpll / (4 * freq)) + 0.5F);
178  //modulation depth = depth (+-depth%)
179  //INCSTEP = round [(215 - 1) x md x PLLN) / (100 x 5 x MODPER)
180  incstep = (uint32_t)((((float)214 * depth * plln) / (100 * 5 * modper)) + 0.5F);
181  spreadsel = 0; //center spread
182  sscgen = 1; //spread spectrum modulation ENABLE
183  sscgr = 0;
184  sscgr |= (modper << RCC_SSCGR_MODPER_Pos) & RCC_SSCGR_MODPER_Msk;
185  sscgr |= (incstep << RCC_SSCGR_INCSTEP_Pos) & RCC_SSCGR_INCSTEP_Msk;
186  sscgr |= (spreadsel << RCC_SSCGR_SPREADSEL_Pos) & RCC_SSCGR_SPREADSEL_Msk;
187  sscgr |= (sscgen << RCC_SSCGR_SSCGEN_Pos) & RCC_SSCGR_SSCGEN_Msk;
188  sys_pll_disable();
189  RCC->SSCGR = sscgr;
190  sys_pll_enable();
191  _dbg0("written SSCGR = 0x%08lx (%lu)", sscgr, sscgr);
192  sscgr = RCC->SSCGR;
193  modper = ((sscgr & RCC_SSCGR_MODPER_Msk) >> RCC_SSCGR_MODPER_Pos);
194  incstep = ((sscgr & RCC_SSCGR_INCSTEP_Msk) >> RCC_SSCGR_INCSTEP_Pos);
195  spreadsel = ((sscgr & RCC_SSCGR_SPREADSEL_Msk) >> RCC_SSCGR_SPREADSEL_Pos);
196  sscgen = ((sscgr & RCC_SSCGR_SSCGEN_Msk) >> RCC_SSCGR_SSCGEN_Pos);
197  _dbg0("readback SSCGR = 0x%08lx (%lu)", sscgr, sscgr);
198  _dbg0(" MODPER = 0x%08lx (%lu)", modper, modper);
199  _dbg0(" INCSTEP = 0x%08lx (%lu)", incstep, incstep);
200  _dbg0(" SPREADSEL = 0x%08lx (%lu)", spreadsel, spreadsel);
201  _dbg0(" SSCGEN = 0x%08lx (%lu)", sscgen, sscgen);
202 }
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◆ sys_sscg_get_config()

int sys_sscg_get_config ( float *  pfreq,
float *  pdepth 
)
204  {
205  return 0;
206 }

◆ sys_spi_set_prescaler()

void sys_spi_set_prescaler ( int  prescaler_num)
230  {
231  int irq = __get_PRIMASK() & 1;
232  if (irq)
233  __disable_irq(); //disable irq while switching clock
235  hspi2.Init.BaudRatePrescaler = _spi_prescaler(prescaler_num);
237  if (irq)
238  __enable_irq();
239 }
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◆ sys_fw_update_is_enabled()

int sys_fw_update_is_enabled ( void  )
241  {
243 }
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◆ sys_fw_update_enable()

void sys_fw_update_enable ( void  )
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◆ sys_fw_update_disable()

void sys_fw_update_disable ( void  )
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◆ sys_fw_update_on_restart_is_enabled()

int sys_fw_update_on_restart_is_enabled ( void  )
253  {
255 }
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◆ sys_fw_update_on_restart_enable()

void sys_fw_update_on_restart_enable ( void  )
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◆ sys_fw_update_on_restart_disable()

void sys_fw_update_on_restart_disable ( void  )
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◆ sys_fw_is_valid()

int sys_fw_is_valid ( void  )
266  {
267  return (*psys_fw_valid != 0) ? 1 : 0;
268 }
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◆ sys_fw_invalidate()

int sys_fw_invalidate ( void  )
271  {
272  uint8_t zero = 0x00;
273  if (sys_flash_is_empty((void *)(psys_fw_valid), 1))
274  if (sys_flash_write((void *)(psys_fw_valid), &zero, 1) != 1)
275  return 0;
276  return (*psys_fw_valid == zero) ? 1 : 0;
277 }
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◆ sys_fw_validate()

int sys_fw_validate ( void  )
281  {
282  return sys_flash_erase_sector(FLASH_SECTOR_11);
283 }
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◆ sys_flash_is_empty()

int sys_flash_is_empty ( void ptr,
int  size 
)
285  {
286  uint8_t *p = (uint8_t *)ptr;
287  for (; size > 0; size--)
288  if (*(p++) != 0xff)
289  return 0;
290  return 1;
291 }
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◆ sys_flash_write()

int sys_flash_write ( void dst,
void src,
int  size 
)
293  {
294  uint8_t *pd = (uint8_t *)dst;
295  uint8_t *ps = (uint8_t *)src;
296  int i = 0;
299  if (status == HAL_OK) {
301  for (; i < size; i++)
302  if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, (uint32_t)(pd++), *(ps++)) != HAL_OK)
303  break;
304  }
305  HAL_FLASH_Lock();
306  return i;
307 }
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◆ sys_flash_erase_sector()

int sys_flash_erase_sector ( unsigned int  sector)
323  {
325  if ((sector < FLASH_SECTOR_0) || (sector > FLASH_SECTOR_11))
326  return 0;
328  if (status == HAL_OK) {
331  }
332  HAL_FLASH_Lock();
333  return (status == HAL_OK) ? 1 : 0;
334 }
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Variable Documentation

◆ ram_data_exchange

volatile data_exchange_t ram_data_exchange
HAL_OK
Definition: stm32f4xx_hal_def.h:57
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition: stm32f4xx_hal_rcc.h:93
HAL_RCC_OscConfig
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_ClkInitTypeDef::SYSCLKSource
uint32_t SYSCLKSource
Definition: stm32f4xx_hal_rcc.h:98
HSE_VALUE
#define HSE_VALUE
Adjust the value of External High Speed oscillator (HSE) used in your application....
Definition: stm32f4xx_hal_conf.h:108
FLASH_FLAG_EOP
#define FLASH_FLAG_EOP
Definition: stm32f4xx_hal_flash.h:132
VOLTAGE_RANGE_3
#define VOLTAGE_RANGE_3
Definition: stm32_hal_legacy.h:317
HAL_FLASH_Unlock
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
_dbg0
#define _dbg0
Definition: dbg.h:31
pd
#define pd
Definition: screen_filebrowser.cpp:39
ram_data_exchange
volatile data_exchange_t ram_data_exchange
hspi2
SPI_HandleTypeDef hspi2
Definition: main.c:81
i
uint8_t i
Definition: screen_test_graph.c:72
st25dv64k_user_write
void st25dv64k_user_write(uint16_t address, uint8_t data)
Definition: st25dv64k.c:103
psys_fw_valid
volatile uint8_t * psys_fw_valid
Definition: sys.cpp:18
FLASH_TYPEPROGRAM_BYTE
#define FLASH_TYPEPROGRAM_BYTE
Definition: stm32f4xx_hal_flash.h:120
RCC_SYSCLKSOURCE_HSE
#define RCC_SYSCLKSOURCE_HSE
Definition: stm32f4xx_hal_rcc.h:220
FLASH_FLAG_PGSERR
#define FLASH_FLAG_PGSERR
Definition: stm32f4xx_hal_flash.h:137
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:55
RCC_PLL_ON
#define RCC_PLL_ON
Definition: stm32f4xx_hal_rcc.h:178
sys_flash_write
int sys_flash_write(void *dst, void *src, int size)
Definition: sys.cpp:293
sys_pll_enable
void sys_pll_enable(void)
Definition: sys.cpp:78
FLASH_FLAG_BSY
#define FLASH_FLAG_BSY
Definition: stm32f4xx_hal_flash.h:141
HAL_FLASH_Lock
HAL_StatusTypeDef HAL_FLASH_Lock(void)
RCC_OscInitTypeDef::PLL
RCC_PLLInitTypeDef PLL
Definition: stm32f4xx_hal_rcc.h:87
FLASH_FLAG_PGAERR
#define FLASH_FLAG_PGAERR
Definition: stm32f4xx_hal_flash.h:135
RCC_PLL_OFF
#define RCC_PLL_OFF
Definition: stm32f4xx_hal_rcc.h:177
HAL_SPI_DeInit
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
RCC_PLLInitTypeDef::PLLState
uint32_t PLLState
Definition: stm32f4xx_hal_rcc_ex.h:65
FLASH_Erase_Sector
void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
FW_UPDATE_ENABLE
#define FW_UPDATE_ENABLE
Definition: shared_config.h:11
HAL_FLASH_Program
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
HAL_SPI_Init
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
__HAL_FLASH_CLEAR_FLAG
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)
Clear the specified FLASH flags.
Definition: stm32f4xx_hal_flash.h:307
FLASH_FLAG_PGPERR
#define FLASH_FLAG_PGPERR
Definition: stm32f4xx_hal_flash.h:136
sys_flash_is_empty
int sys_flash_is_empty(void *ptr, int size)
Definition: sys.cpp:285
HAL_RCC_GetOscConfig
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
uint8_t
const uint8_t[]
Definition: 404_html.c:3
_spi_prescaler
uint32_t _spi_prescaler(int prescaler_num)
Definition: sys.cpp:208
FLASH_FLAG_OPERR
#define FLASH_FLAG_OPERR
Definition: stm32f4xx_hal_flash.h:133
__SPI_HandleTypeDef::Init
SPI_InitTypeDef Init
Definition: stm32f4xx_hal_spi.h:124
sys_pll_disable
void sys_pll_disable(void)
Definition: sys.cpp:57
sys_calc_flash_latency
int sys_calc_flash_latency(int freq)
Definition: sys.cpp:34
sys_flash_erase_sector
int sys_flash_erase_sector(unsigned int sector)
Definition: sys.cpp:323
status
static status_t status
Definition: filament_sensor.c:37
data_exchange_t::fw_update_flag
uint8_t fw_update_flag
Definition: shared_config.h:20
RCC_SYSCLKSOURCE_PLLCLK
#define RCC_SYSCLKSOURCE_PLLCLK
Definition: stm32f4xx_hal_rcc.h:221
SPI_InitTypeDef::BaudRatePrescaler
uint32_t BaudRatePrescaler
Definition: stm32f4xx_hal_spi.h:84
HAL_RCC_ClockConfig
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
FW_UPDATE_FLAG_ADDRESS
#define FW_UPDATE_FLAG_ADDRESS
Definition: new_eeprom.h:20
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.
Definition: stm32f4xx_hal_rcc.h:67
st25dv64k_user_read
uint8_t st25dv64k_user_read(uint16_t address)
Definition: st25dv64k.c:93
RCC_PLLInitTypeDef::PLLN
uint32_t PLLN
Definition: stm32f4xx_hal_rcc_ex.h:74
HAL_RCC_GetClockConfig
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
FLASH_FLAG_WRPERR
#define FLASH_FLAG_WRPERR
Definition: stm32f4xx_hal_flash.h:134
sys_pll_freq
int sys_pll_freq
Definition: sys.cpp:12
FW_UPDATE_DISABLE
#define FW_UPDATE_DISABLE
Definition: shared_config.h:12
size
static png_bytep size_t size
Definition: pngwrite.c:2170