ADC Private Macros

Collaboration diagram for ADC Private Macros:

Macros
#define	ADC_IS_ENABLE(__HANDLE__)
	Verification of ADC state: enabled or disabled. More...
#define	ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)   (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
	Test if conversion trigger of regular group is software start or external trigger. More...
#define	ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)   (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
	Test if conversion trigger of injected group is software start or external trigger. More...
#define	ADC_STATE_CLR_SET   MODIFY_REG
	Simultaneously clears and sets specific bits of the handle State. More...
#define	ADC_CLEAR_ERRORCODE(__HANDLE__)   ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
	Clear ADC error code (set it to error code: "no error") More...
#define	IS_ADC_CLOCKPRESCALER(ADC_CLOCK)
#define	IS_ADC_SAMPLING_DELAY(DELAY)
#define	IS_ADC_RESOLUTION(RESOLUTION)
#define	IS_ADC_EXT_TRIG_EDGE(EDGE)
#define	IS_ADC_EXT_TRIG(REGTRIG)
#define	IS_ADC_DATA_ALIGN(ALIGN)
#define	IS_ADC_SAMPLE_TIME(TIME)
#define	IS_ADC_EOCSelection(EOCSelection)
#define	IS_ADC_EVENT_TYPE(EVENT)
#define	IS_ADC_ANALOG_WATCHDOG(WATCHDOG)
#define	IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE)
#define	IS_ADC_THRESHOLD(THRESHOLD)   ((THRESHOLD) <= 0xFFFU)
#define	IS_ADC_REGULAR_LENGTH(LENGTH)   (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
#define	IS_ADC_REGULAR_RANK(RANK)   (((RANK) >= 1U) && ((RANK) <= (16U)))
#define	IS_ADC_REGULAR_DISC_NUMBER(NUMBER)   (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
#define	IS_ADC_RANGE(RESOLUTION, ADC_VALUE)
#define	ADC_SQR1(_NbrOfConversion_)   (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
	Set ADC Regular channel sequence length. More...
#define	ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_)   ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
	Set the ADC's sample time for channel numbers between 10 and 18. More...
#define	ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_)   ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
	Set the ADC's sample time for channel numbers between 0 and 9. More...
#define	ADC_SQR3_RK(_CHANNELNB_, _RANKNB_)   (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
	Set the selected regular channel rank for rank between 1 and 6. More...
#define	ADC_SQR2_RK(_CHANNELNB_, _RANKNB_)   (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
	Set the selected regular channel rank for rank between 7 and 12. More...
#define	ADC_SQR1_RK(_CHANNELNB_, _RANKNB_)   (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
	Set the selected regular channel rank for rank between 13 and 16. More...
#define	ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_)   ((_CONTINUOUS_MODE_) << 1U)
	Enable ADC continuous conversion mode. More...
#define	ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_)   (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos)
	Configures the number of discontinuous conversions for the regular group channels. More...
#define	ADC_CR1_SCANCONV(_SCANCONV_MODE_)   ((_SCANCONV_MODE_) << 8U)
	Enable ADC scan mode. More...
#define	ADC_CR2_EOCSelection(_EOCSelection_MODE_)   ((_EOCSelection_MODE_) << 10U)
	Enable the ADC end of conversion selection. More...
#define	ADC_CR2_DMAContReq(_DMAContReq_MODE_)   ((_DMAContReq_MODE_) << 9U)
	Enable the ADC DMA continuous request. More...
#define	ADC_GET_RESOLUTION(__HANDLE__)   (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
	Return resolution bits in CR1 register. More...

Detailed Description

Macro Definition Documentation

ADC_IS_ENABLE

#define ADC_IS_ENABLE

(

__HANDLE__

)

Value:

((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
  ) ? SET : RESET)

Verification of ADC state: enabled or disabled.

Parameters

<strong>HANDLE</strong>

ADC handle

Return values

SET	(ADC enabled) or RESET (ADC disabled)

ADC_IS_SOFTWARE_START_REGULAR

#define ADC_IS_SOFTWARE_START_REGULAR

(

__HANDLE__

)

(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)

Test if conversion trigger of regular group is software start or external trigger.

Parameters

<strong>HANDLE</strong>

ADC handle

Return values

SET	(software start) or RESET (external trigger)

ADC_IS_SOFTWARE_START_INJECTED

#define ADC_IS_SOFTWARE_START_INJECTED

(

__HANDLE__

)

(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)

Test if conversion trigger of injected group is software start or external trigger.

Parameters

<strong>HANDLE</strong>

ADC handle

Return values

SET	(software start) or RESET (external trigger)

ADC_STATE_CLR_SET

#define ADC_STATE_CLR_SET   MODIFY_REG

Simultaneously clears and sets specific bits of the handle State.

Note

: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.

Return values

None

ADC_CLEAR_ERRORCODE

#define ADC_CLEAR_ERRORCODE

(

__HANDLE__

)

((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to error code: "no error")

Parameters

<strong>HANDLE</strong>

ADC handle

Return values

None

IS_ADC_CLOCKPRESCALER

#define IS_ADC_CLOCKPRESCALER

(

ADC_CLOCK

)

Value:

(((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))

IS_ADC_SAMPLING_DELAY

#define IS_ADC_SAMPLING_DELAY

(

DELAY

)

Value:

(((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))

IS_ADC_RESOLUTION

#define IS_ADC_RESOLUTION

(

RESOLUTION

)

Value:

(((RESOLUTION) == ADC_RESOLUTION_12B) || \
                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \
                                       ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
                                       ((RESOLUTION) == ADC_RESOLUTION_6B))

IS_ADC_EXT_TRIG_EDGE

#define IS_ADC_EXT_TRIG_EDGE

(

EDGE

)

Value:

(((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))

IS_ADC_EXT_TRIG

#define IS_ADC_EXT_TRIG

(

REGTRIG

)

Value:

(((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
                                  ((REGTRIG) == ADC_SOFTWARE_START))

IS_ADC_DATA_ALIGN

#define IS_ADC_DATA_ALIGN

(

ALIGN

)

Value:

(((ALIGN) == ADC_DATAALIGN_RIGHT) || \
                                  ((ALIGN) == ADC_DATAALIGN_LEFT))

IS_ADC_SAMPLE_TIME

#define IS_ADC_SAMPLE_TIME

(

TIME

)

Value:

(((TIME) == ADC_SAMPLETIME_3CYCLES)   || \
                                  ((TIME) == ADC_SAMPLETIME_15CYCLES)  || \
                                  ((TIME) == ADC_SAMPLETIME_28CYCLES)  || \
                                  ((TIME) == ADC_SAMPLETIME_56CYCLES)  || \
                                  ((TIME) == ADC_SAMPLETIME_84CYCLES)  || \
                                  ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
                                  ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
                                  ((TIME) == ADC_SAMPLETIME_480CYCLES))

IS_ADC_EOCSelection

#define IS_ADC_EOCSelection

(

EOCSelection

)

Value:

(((EOCSelection) == ADC_EOC_SINGLE_CONV)   || \
                                           ((EOCSelection) == ADC_EOC_SEQ_CONV)  || \
                                           ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))

IS_ADC_EVENT_TYPE

#define IS_ADC_EVENT_TYPE

(

EVENT

)

Value:

(((EVENT) == ADC_AWD_EVENT) || \
                                  ((EVENT) == ADC_OVR_EVENT))

IS_ADC_ANALOG_WATCHDOG

#define IS_ADC_ANALOG_WATCHDOG

(

WATCHDOG

)

Value:

(((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))

IS_ADC_CHANNELS_TYPE

#define IS_ADC_CHANNELS_TYPE

(

CHANNEL_TYPE

)

Value:

(((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
                                            ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
                                            ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))

IS_ADC_THRESHOLD

#define IS_ADC_THRESHOLD

(

THRESHOLD

)

((THRESHOLD) <= 0xFFFU)

IS_ADC_REGULAR_LENGTH

#define IS_ADC_REGULAR_LENGTH

(

LENGTH

)

(((LENGTH) >= 1U) && ((LENGTH) <= 16U))

IS_ADC_REGULAR_RANK

#define IS_ADC_REGULAR_RANK

(

RANK

)

(((RANK) >= 1U) && ((RANK) <= (16U)))

IS_ADC_REGULAR_DISC_NUMBER

#define IS_ADC_REGULAR_DISC_NUMBER

(

NUMBER

)

(((NUMBER) >= 1U) && ((NUMBER) <= 8U))

IS_ADC_RANGE

#define IS_ADC_RANGE	(		RESOLUTION,
			ADC_VALUE
	)

Value:

((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= 0x00FFU)) || \
    (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= 0x003FU)))

ADC_SQR1

#define ADC_SQR1

(

_NbrOfConversion_

)

(((_NbrOfConversion_) - (uint8_t)1U) << 20U)

Set ADC Regular channel sequence length.

Parameters

<em>NbrOfConversion</em>

Regular channel sequence length.

Return values

None

ADC_SMPR1

#define ADC_SMPR1	(		_SAMPLETIME_,
			_CHANNELNB_
	)		((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))

Set the ADC's sample time for channel numbers between 10 and 18.

Parameters

<em>SAMPLETIME</em>	Sample time parameter.
<em>CHANNELNB</em>	Channel number.

Return values

None

ADC_SMPR2

#define ADC_SMPR2	(		_SAMPLETIME_,
			_CHANNELNB_
	)		((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))

Set the ADC's sample time for channel numbers between 0 and 9.

Parameters

<em>SAMPLETIME</em>	Sample time parameter.
<em>CHANNELNB</em>	Channel number.

Return values

None

ADC_SQR3_RK

#define ADC_SQR3_RK	(		_CHANNELNB_,
			_RANKNB_
	)		(((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))

Set the selected regular channel rank for rank between 1 and 6.

Parameters

<em>CHANNELNB</em>	Channel number.
<em>RANKNB</em>	Rank number.

Return values

None

ADC_SQR2_RK

#define ADC_SQR2_RK	(		_CHANNELNB_,
			_RANKNB_
	)		(((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))

Set the selected regular channel rank for rank between 7 and 12.

Parameters

<em>CHANNELNB</em>	Channel number.
<em>RANKNB</em>	Rank number.

Return values

None

ADC_SQR1_RK

#define ADC_SQR1_RK	(		_CHANNELNB_,
			_RANKNB_
	)		(((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))

Set the selected regular channel rank for rank between 13 and 16.

Parameters

<em>CHANNELNB</em>	Channel number.
<em>RANKNB</em>	Rank number.

Return values

None

ADC_CR2_CONTINUOUS

#define ADC_CR2_CONTINUOUS

(

_CONTINUOUS_MODE_

)

((_CONTINUOUS_MODE_) << 1U)

Enable ADC continuous conversion mode.

Parameters

<em>CONTINUOUS_MODE</em>

Continuous mode.

Return values

None

ADC_CR1_DISCONTINUOUS

#define ADC_CR1_DISCONTINUOUS

(

_NBR_DISCONTINUOUSCONV_

)

(((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos)

Configures the number of discontinuous conversions for the regular group channels.

Parameters

<em>NBR_DISCONTINUOUSCONV</em>

Number of discontinuous conversions.

Return values

None

ADC_CR1_SCANCONV

#define ADC_CR1_SCANCONV

(

_SCANCONV_MODE_

)

((_SCANCONV_MODE_) << 8U)

Enable ADC scan mode.

Parameters

<em>SCANCONV_MODE</em>

Scan conversion mode.

Return values

None

ADC_CR2_EOCSelection

#define ADC_CR2_EOCSelection

(

_EOCSelection_MODE_

)

((_EOCSelection_MODE_) << 10U)

Enable the ADC end of conversion selection.

Parameters

<em>EOCSelection_MODE</em>

End of conversion selection mode.

Return values

None

ADC_CR2_DMAContReq

#define ADC_CR2_DMAContReq

(

_DMAContReq_MODE_

)

((_DMAContReq_MODE_) << 9U)

Enable the ADC DMA continuous request.

Parameters

<em>DMAContReq_MODE</em>

DMA continuous request mode.

Return values

None

ADC_GET_RESOLUTION

#define ADC_GET_RESOLUTION

(

__HANDLE__

)

(((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)

Return resolution bits in CR1 register.

Parameters

<strong>HANDLE</strong>

ADC handle

Return values

None