Prusa MINI Firmware overview
stm32f4xx_hal_adc.h
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1 /**
2  ******************************************************************************
3  * @file stm32f4xx_hal_adc.h
4  * @author MCD Application Team
5  * @brief Header file containing functions prototypes of ADC HAL library.
6  ******************************************************************************
7  * @attention
8  *
9  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10  *
11  * Redistribution and use in source and binary forms, with or without modification,
12  * are permitted provided that the following conditions are met:
13  * 1. Redistributions of source code must retain the above copyright notice,
14  * this list of conditions and the following disclaimer.
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16  * this list of conditions and the following disclaimer in the documentation
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18  * 3. Neither the name of STMicroelectronics nor the names of its contributors
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20  * without specific prior written permission.
21  *
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33  ******************************************************************************
34  */
35 
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_ADC_H
38 #define __STM32F4xx_ADC_H
39 
40 #ifdef __cplusplus
41  extern "C" {
42 #endif
43 
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f4xx_hal_def.h"
46 
47 /** @addtogroup STM32F4xx_HAL_Driver
48  * @{
49  */
50 
51 /** @addtogroup ADC
52  * @{
53  */
54 
55 /* Exported types ------------------------------------------------------------*/
56 /** @defgroup ADC_Exported_Types ADC Exported Types
57  * @{
58  */
59 
60 /**
61  * @brief Structure definition of ADC and regular group initialization
62  * @note Parameters of this structure are shared within 2 scopes:
63  * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
64  * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
65  * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
66  * ADC state can be either:
67  * - For all parameters: ADC disabled
68  * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
69  * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
70  * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
71  * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
72  */
73 typedef struct
74 {
75  uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
76  all the ADCs.
77  This parameter can be a value of @ref ADC_ClockPrescaler */
78  uint32_t Resolution; /*!< Configures the ADC resolution.
79  This parameter can be a value of @ref ADC_Resolution */
80  uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
81  or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
82  This parameter can be a value of @ref ADC_Data_align */
83  uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
84  This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
85  If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
86  Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
87  If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
88  Scan direction is upward: from rank1 to rank 'n'.
89  This parameter can be set to ENABLE or DISABLE */
90  uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
91  This parameter can be a value of @ref ADC_EOCSelection.
92  Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
93  Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
94  or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
95  Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
96  If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
97  uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
98  after the selected trigger occurred (software start or external trigger).
99  This parameter can be set to ENABLE or DISABLE. */
100  uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
101  To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
102  This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
103  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
104  Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
105  Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
106  This parameter can be set to ENABLE or DISABLE. */
107  uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
108  If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
109  This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
110  uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
111  If set to ADC_SOFTWARE_START, external triggers are disabled.
112  If set to external trigger source, triggering is on event rising edge by default.
113  This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
114  uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
115  If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
116  This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
117  uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
118  or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
119  Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
120  Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
121  This parameter can be set to ENABLE or DISABLE. */
122 }ADC_InitTypeDef;
123 
124 
125 
126 /**
127  * @brief Structure definition of ADC channel for regular group
128  * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
129  * ADC can be either disabled or enabled without conversion on going on regular group.
130  */
131 typedef struct
132 {
133  uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
134  This parameter can be a value of @ref ADC_channels */
135  uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
136  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
137  uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
138  Unit: ADC clock cycles
139  Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
140  This parameter can be a value of @ref ADC_sampling_times
141  Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
142  If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
143  Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
144  sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
145  Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
146  uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
147 }ADC_ChannelConfTypeDef;
148 
149 /**
150  * @brief ADC Configuration multi-mode structure definition
151  */
152 typedef struct
153 {
154  uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
155  This parameter can be a value of @ref ADC_analog_watchdog_selection */
156  uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
157  This parameter must be a 12-bit value. */
158  uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
159  This parameter must be a 12-bit value. */
160  uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
161  This parameter has an effect only if watchdog mode is configured on single channel
162  This parameter can be a value of @ref ADC_channels */
163  uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
164  is interrupt mode or in polling mode.
165  This parameter can be set to ENABLE or DISABLE */
166  uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
167 }ADC_AnalogWDGConfTypeDef;
168 
169 /**
170  * @brief HAL ADC state machine: ADC states definition (bitfields)
171  */
172 /* States of ADC global scope */
173 #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
174 #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
175 #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
176 #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
177 
178 /* States of ADC errors */
179 #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
180 #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
181 #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
182 
183 /* States of ADC group regular */
184 #define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
185  external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
186 #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
187 #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */
188 
189 /* States of ADC group injected */
190 #define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
191  external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
192 #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
193 
194 /* States of ADC analog watchdogs */
195 #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
196 #define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */
197 #define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */
198 
199 /* States of ADC multi-mode */
200 #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
201 
202 
203 /**
204  * @brief ADC handle Structure definition
205  */
206 typedef struct
207 {
208  ADC_TypeDef *Instance; /*!< Register base address */
209 
210  ADC_InitTypeDef Init; /*!< ADC required parameters */
211 
212  __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
213 
214  DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
215 
216  HAL_LockTypeDef Lock; /*!< ADC locking object */
217 
218  __IO uint32_t State; /*!< ADC communication state */
219 
220  __IO uint32_t ErrorCode; /*!< ADC Error code */
221 }ADC_HandleTypeDef;
222 /**
223  * @}
224  */
225 
226 /* Exported constants --------------------------------------------------------*/
227 /** @defgroup ADC_Exported_Constants ADC Exported Constants
228  * @{
229  */
230 
231 /** @defgroup ADC_Error_Code ADC Error Code
232  * @{
233  */
234 #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
235 #define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
236  enable/disable, erroneous state */
237 #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
238 #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
239 /**
240  * @}
241  */
242 
243 
244 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
245  * @{
246  */
247 #define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U
248 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
249 #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
250 #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
251 /**
252  * @}
253  */
254 
255 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
256  * @{
257  */
258 #define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U
259 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
260 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
261 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
262 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
263 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
264 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
265 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
266 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
267 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
268 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
269 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
270 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
271 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
272 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
273 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
274 /**
275  * @}
276  */
277 
278 /** @defgroup ADC_Resolution ADC Resolution
279  * @{
280  */
281 #define ADC_RESOLUTION_12B 0x00000000U
282 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
283 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
284 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
285 /**
286  * @}
287  */
288 
289 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
290  * @{
291  */
292 #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
293 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
294 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
295 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
296 /**
297  * @}
298  */
299 
300 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
301  * @{
302  */
303 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
304 /* compatibility with other STM32 devices. */
305 #define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U
306 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
307 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
308 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
309 #define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
310 #define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
311 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
312 #define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
313 #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
314 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
315 #define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
316 #define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
317 #define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
318 #define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
319 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
320 #define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
321 #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U)
322 /**
323  * @}
324  */
325 
326 /** @defgroup ADC_Data_align ADC Data Align
327  * @{
328  */
329 #define ADC_DATAALIGN_RIGHT 0x00000000U
330 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
331 /**
332  * @}
333  */
334 
335 /** @defgroup ADC_channels ADC Common Channels
336  * @{
337  */
338 #define ADC_CHANNEL_0 0x00000000U
339 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
340 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
341 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
342 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
343 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
344 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
345 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
346 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
347 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
348 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
349 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
350 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
351 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
352 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
353 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
354 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
355 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
356 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
357 
358 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
359 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
360 /**
361  * @}
362  */
363 
364 /** @defgroup ADC_sampling_times ADC Sampling Times
365  * @{
366  */
367 #define ADC_SAMPLETIME_3CYCLES 0x00000000U
368 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
369 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
370 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
371 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
372 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
373 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
374 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
375 /**
376  * @}
377  */
378 
379  /** @defgroup ADC_EOCSelection ADC EOC Selection
380  * @{
381  */
382 #define ADC_EOC_SEQ_CONV 0x00000000U
383 #define ADC_EOC_SINGLE_CONV 0x00000001U
384 #define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */
385 /**
386  * @}
387  */
388 
389 /** @defgroup ADC_Event_type ADC Event Type
390  * @{
391  */
392 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
393 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
394 /**
395  * @}
396  */
397 
398 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
399  * @{
400  */
401 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
402 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
403 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
404 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
405 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
406 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
407 #define ADC_ANALOGWATCHDOG_NONE 0x00000000U
408 /**
409  * @}
410  */
411 
412 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
413  * @{
414  */
415 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
416 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
417 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
418 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
419 /**
420  * @}
421  */
422 
423 /** @defgroup ADC_flags_definition ADC Flags Definition
424  * @{
425  */
426 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
427 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
428 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
429 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
430 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
431 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
432 /**
433  * @}
434  */
435 
436 /** @defgroup ADC_channels_type ADC Channels Type
437  * @{
438  */
439 #define ADC_ALL_CHANNELS 0x00000001U
440 #define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */
441 #define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
442 /**
443  * @}
444  */
445 
446 /**
447  * @}
448  */
449 
450 /* Exported macro ------------------------------------------------------------*/
451 /** @defgroup ADC_Exported_Macros ADC Exported Macros
452  * @{
453  */
454 
455 /** @brief Reset ADC handle state
456  * @param __HANDLE__ ADC handle
457  * @retval None
458  */
459 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
460 
461 /**
462  * @brief Enable the ADC peripheral.
463  * @param __HANDLE__ ADC handle
464  * @retval None
465  */
466 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
467 
468 /**
469  * @brief Disable the ADC peripheral.
470  * @param __HANDLE__ ADC handle
471  * @retval None
472  */
473 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
474 
475 /**
476  * @brief Enable the ADC end of conversion interrupt.
477  * @param __HANDLE__ specifies the ADC Handle.
478  * @param __INTERRUPT__ ADC Interrupt.
479  * @retval None
480  */
481 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
482 
483 /**
484  * @brief Disable the ADC end of conversion interrupt.
485  * @param __HANDLE__ specifies the ADC Handle.
486  * @param __INTERRUPT__ ADC interrupt.
487  * @retval None
488  */
489 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
490 
491 /** @brief Check if the specified ADC interrupt source is enabled or disabled.
492  * @param __HANDLE__ specifies the ADC Handle.
493  * @param __INTERRUPT__ specifies the ADC interrupt source to check.
494  * @retval The new state of __IT__ (TRUE or FALSE).
495  */
496 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
497 
498 /**
499  * @brief Clear the ADC's pending flags.
500  * @param __HANDLE__ specifies the ADC Handle.
501  * @param __FLAG__ ADC flag.
502  * @retval None
503  */
504 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
505 
506 /**
507  * @brief Get the selected ADC's flag status.
508  * @param __HANDLE__ specifies the ADC Handle.
509  * @param __FLAG__ ADC flag.
510  * @retval None
511  */
512 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
513 
514 /**
515  * @}
516  */
517 
518 /* Include ADC HAL Extension module */
519 #include "stm32f4xx_hal_adc_ex.h"
520 
521 /* Exported functions --------------------------------------------------------*/
522 /** @addtogroup ADC_Exported_Functions
523  * @{
524  */
525 
526 /** @addtogroup ADC_Exported_Functions_Group1
527  * @{
528  */
529 /* Initialization/de-initialization functions ***********************************/
530 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
531 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
532 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
533 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
534 /**
535  * @}
536  */
537 
538 /** @addtogroup ADC_Exported_Functions_Group2
539  * @{
540  */
541 /* I/O operation functions ******************************************************/
542 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
543 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
544 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
545 
546 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
547 
548 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
549 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
550 
551 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
552 
553 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
554 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
555 
556 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
557 
558 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
559 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
560 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
561 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
562 /**
563  * @}
564  */
565 
566 /** @addtogroup ADC_Exported_Functions_Group3
567  * @{
568  */
569 /* Peripheral Control functions *************************************************/
570 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
571 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
572 /**
573  * @}
574  */
575 
576 /** @addtogroup ADC_Exported_Functions_Group4
577  * @{
578  */
579 /* Peripheral State functions ***************************************************/
580 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
581 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
582 /**
583  * @}
584  */
585 
586 /**
587  * @}
588  */
589 /* Private types -------------------------------------------------------------*/
590 /* Private variables ---------------------------------------------------------*/
591 /* Private constants ---------------------------------------------------------*/
592 /** @defgroup ADC_Private_Constants ADC Private Constants
593  * @{
594  */
595 /* Delay for ADC stabilization time. */
596 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
597 /* Unit: us */
598 #define ADC_STAB_DELAY_US 3U
599 /* Delay for temperature sensor stabilization time. */
600 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
601 /* Unit: us */
602 #define ADC_TEMPSENSOR_DELAY_US 10U
603 /**
604  * @}
605  */
606 
607 /* Private macro ------------------------------------------------------------*/
608 
609 /** @defgroup ADC_Private_Macros ADC Private Macros
610  * @{
611  */
612 /* Macro reserved for internal HAL driver usage, not intended to be used in
613  code of final user */
614 
615 /**
616  * @brief Verification of ADC state: enabled or disabled
617  * @param __HANDLE__ ADC handle
618  * @retval SET (ADC enabled) or RESET (ADC disabled)
619  */
620 #define ADC_IS_ENABLE(__HANDLE__) \
621  ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
622  ) ? SET : RESET)
623 
624 /**
625  * @brief Test if conversion trigger of regular group is software start
626  * or external trigger.
627  * @param __HANDLE__ ADC handle
628  * @retval SET (software start) or RESET (external trigger)
629  */
630 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
631  (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
632 
633 /**
634  * @brief Test if conversion trigger of injected group is software start
635  * or external trigger.
636  * @param __HANDLE__ ADC handle
637  * @retval SET (software start) or RESET (external trigger)
638  */
639 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
640  (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
641 
642 /**
643  * @brief Simultaneously clears and sets specific bits of the handle State
644  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
645  * the first parameter is the ADC handle State, the second parameter is the
646  * bit field to clear, the third and last parameter is the bit field to set.
647  * @retval None
648  */
649 #define ADC_STATE_CLR_SET MODIFY_REG
650 
651 /**
652  * @brief Clear ADC error code (set it to error code: "no error")
653  * @param __HANDLE__ ADC handle
654  * @retval None
655  */
656 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
657  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
658 
659 
660 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
661  ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
662  ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
663  ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
664 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
665  ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
666  ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
667  ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
668  ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
669  ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
670  ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
671  ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
672  ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
673  ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
674  ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
675  ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
676  ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
677  ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
678  ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
679  ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
680 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
681  ((RESOLUTION) == ADC_RESOLUTION_10B) || \
682  ((RESOLUTION) == ADC_RESOLUTION_8B) || \
683  ((RESOLUTION) == ADC_RESOLUTION_6B))
684 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
685  ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
686  ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
687  ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
688 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
689  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
690  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
691  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
692  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
693  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
694  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
695  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
696  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
697  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
698  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
699  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
700  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
701  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
702  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
703  ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
704  ((REGTRIG) == ADC_SOFTWARE_START))
705 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
706  ((ALIGN) == ADC_DATAALIGN_LEFT))
707 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
708  ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
709  ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
710  ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
711  ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
712  ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
713  ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
714  ((TIME) == ADC_SAMPLETIME_480CYCLES))
715 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \
716  ((EOCSelection) == ADC_EOC_SEQ_CONV) || \
717  ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
718 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
719  ((EVENT) == ADC_OVR_EVENT))
720 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
721  ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
722  ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
723  ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
724  ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
725  ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
726  ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
727 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
728  ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
729  ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
730 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
731 
732 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
733 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U)))
734 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
735 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
736  ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
737  (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
738  (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \
739  (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU)))
740 
741 /**
742  * @brief Set ADC Regular channel sequence length.
743  * @param _NbrOfConversion_ Regular channel sequence length.
744  * @retval None
745  */
746 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
747 
748 /**
749  * @brief Set the ADC's sample time for channel numbers between 10 and 18.
750  * @param _SAMPLETIME_ Sample time parameter.
751  * @param _CHANNELNB_ Channel number.
752  * @retval None
753  */
754 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
755 
756 /**
757  * @brief Set the ADC's sample time for channel numbers between 0 and 9.
758  * @param _SAMPLETIME_ Sample time parameter.
759  * @param _CHANNELNB_ Channel number.
760  * @retval None
761  */
762 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
763 
764 /**
765  * @brief Set the selected regular channel rank for rank between 1 and 6.
766  * @param _CHANNELNB_ Channel number.
767  * @param _RANKNB_ Rank number.
768  * @retval None
769  */
770 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
771 
772 /**
773  * @brief Set the selected regular channel rank for rank between 7 and 12.
774  * @param _CHANNELNB_ Channel number.
775  * @param _RANKNB_ Rank number.
776  * @retval None
777  */
778 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
779 
780 /**
781  * @brief Set the selected regular channel rank for rank between 13 and 16.
782  * @param _CHANNELNB_ Channel number.
783  * @param _RANKNB_ Rank number.
784  * @retval None
785  */
786 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
787 
788 /**
789  * @brief Enable ADC continuous conversion mode.
790  * @param _CONTINUOUS_MODE_ Continuous mode.
791  * @retval None
792  */
793 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
794 
795 /**
796  * @brief Configures the number of discontinuous conversions for the regular group channels.
797  * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.
798  * @retval None
799  */
800 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos)
801 
802 /**
803  * @brief Enable ADC scan mode.
804  * @param _SCANCONV_MODE_ Scan conversion mode.
805  * @retval None
806  */
807 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
808 
809 /**
810  * @brief Enable the ADC end of conversion selection.
811  * @param _EOCSelection_MODE_ End of conversion selection mode.
812  * @retval None
813  */
814 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
815 
816 /**
817  * @brief Enable the ADC DMA continuous request.
818  * @param _DMAContReq_MODE_ DMA continuous request mode.
819  * @retval None
820  */
821 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
822 
823 /**
824  * @brief Return resolution bits in CR1 register.
825  * @param __HANDLE__ ADC handle
826  * @retval None
827  */
828 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
829 
830 /**
831  * @}
832  */
833 
834 /* Private functions ---------------------------------------------------------*/
835 /** @defgroup ADC_Private_Functions ADC Private Functions
836  * @{
837  */
838 
839 /**
840  * @}
841  */
842 
843 /**
844  * @}
845  */
846 
847 /**
848  * @}
849  */
850 
851 #ifdef __cplusplus
852 }
853 #endif
854 
855 #endif /*__STM32F4xx_ADC_H */
856 
857 
858 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_ADC_GetState
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
ADC_InitTypeDef::ContinuousConvMode
uint32_t ContinuousConvMode
Definition: stm32f4xx_hal_adc.h:97
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
ADC_AnalogWDGConfTypeDef::WatchdogNumber
uint32_t WatchdogNumber
Definition: stm32f4xx_hal_adc.h:166
ADC_AnalogWDGConfTypeDef::ITMode
uint32_t ITMode
Definition: stm32f4xx_hal_adc.h:163
HAL_ADC_Start
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
HAL_ADC_MspDeInit
void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
ADC MSP De-Initialization This function freeze the hardware resources used in this example.
Definition: stm32f4xx_hal_msp.c:158
HAL_ADC_IRQHandler
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
HAL_ADC_AnalogWDGConfig
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
ADC_ChannelConfTypeDef::Offset
uint32_t Offset
Definition: stm32f4xx_hal_adc.h:146
ADC_InitTypeDef::DMAContinuousRequests
uint32_t DMAContinuousRequests
Definition: stm32f4xx_hal_adc.h:117
HAL_ADC_MspInit
void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
ADC MSP Initialization This function configures the hardware resources used in this example.
Definition: stm32f4xx_hal_msp.c:116
HAL_ADC_GetValue
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
ADC_ChannelConfTypeDef::Channel
uint32_t Channel
Definition: stm32f4xx_hal_adc.h:133
ADC_ChannelConfTypeDef::Rank
uint32_t Rank
Definition: stm32f4xx_hal_adc.h:135
HAL_ADC_DeInit
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
HAL_ADC_Stop_DMA
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:55
ADC_AnalogWDGConfTypeDef::WatchdogMode
uint32_t WatchdogMode
Definition: stm32f4xx_hal_adc.h:154
HAL_ADC_ErrorCallback
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
HAL_ADC_ConvCpltCallback
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
HAL_ADC_ConvHalfCpltCallback
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group.
Definition: stm32f4xx_hal_adc.h:131
HAL_ADC_Init
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
ADC_InitTypeDef::DataAlign
uint32_t DataAlign
Definition: stm32f4xx_hal_adc.h:80
ADC_InitTypeDef::Resolution
uint32_t Resolution
Definition: stm32f4xx_hal_adc.h:78
HAL_ADC_GetError
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
ADC_AnalogWDGConfTypeDef::Channel
uint32_t Channel
Definition: stm32f4xx_hal_adc.h:160
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f4xx_hal_dma.h:155
HAL_ADC_Stop
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
ADC_InitTypeDef::ClockPrescaler
uint32_t ClockPrescaler
Definition: stm32f4xx_hal_adc.h:75
ADC_ChannelConfTypeDef::SamplingTime
uint32_t SamplingTime
Definition: stm32f4xx_hal_adc.h:137
ADC_AnalogWDGConfTypeDef
ADC Configuration multi-mode structure definition.
Definition: stm32f4xx_hal_adc.h:152
ADC_InitTypeDef
Structure definition of ADC and regular group initialization.
Definition: stm32f4xx_hal_adc.h:73
ADC_HandleTypeDef
ADC handle Structure definition.
Definition: stm32f4xx_hal_adc.h:208
ADC_InitTypeDef::NbrOfDiscConversion
uint32_t NbrOfDiscConversion
Definition: stm32f4xx_hal_adc.h:107
HAL_ADC_Start_DMA
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
HAL_ADC_PollForConversion
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
HAL_ADC_Start_IT
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
ADC_InitTypeDef::NbrOfConversion
uint32_t NbrOfConversion
Definition: stm32f4xx_hal_adc.h:100
ADC_InitTypeDef::EOCSelection
uint32_t EOCSelection
Definition: stm32f4xx_hal_adc.h:90
ADC_InitTypeDef::DiscontinuousConvMode
uint32_t DiscontinuousConvMode
Definition: stm32f4xx_hal_adc.h:103
ADC_InitTypeDef::ExternalTrigConvEdge
uint32_t ExternalTrigConvEdge
Definition: stm32f4xx_hal_adc.h:114
HAL_ADC_ConfigChannel
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
HAL_ADC_Stop_IT
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
stm32f4xx_hal_adc_ex.h
Header file of ADC HAL module.
ADC_InitTypeDef::ScanConvMode
uint32_t ScanConvMode
Definition: stm32f4xx_hal_adc.h:83
ADC_AnalogWDGConfTypeDef::LowThreshold
uint32_t LowThreshold
Definition: stm32f4xx_hal_adc.h:158
HAL_ADC_LevelOutOfWindowCallback
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f4xx_hal_def.h:66
HAL_ADC_PollForEvent
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
ADC_InitTypeDef::ExternalTrigConv
uint32_t ExternalTrigConv
Definition: stm32f4xx_hal_adc.h:110
ADC_AnalogWDGConfTypeDef::HighThreshold
uint32_t HighThreshold
Definition: stm32f4xx_hal_adc.h:156