Prusa MINI Firmware overview
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33 #include "../../inc/MarlinConfig.h"
39 #if HAS_DRIVER(TMC26X)
52 #define X_ENABLE_INIT SET_OUTPUT(X_ENABLE_PIN)
53 #define X_ENABLE_WRITE(STATE) WRITE(X_ENABLE_PIN,STATE)
54 #define X_ENABLE_READ() READ(X_ENABLE_PIN)
57 #define X_DIR_INIT SET_OUTPUT(X_DIR_PIN)
58 #define X_DIR_WRITE(STATE) WRITE(X_DIR_PIN,STATE)
59 #define X_DIR_READ() READ(X_DIR_PIN)
61 #define X_STEP_INIT SET_OUTPUT(X_STEP_PIN)
63 #define X_STEP_WRITE(STATE) WRITE(X_STEP_PIN,STATE)
65 #define X_STEP_READ READ(X_STEP_PIN)
69 #define Y_ENABLE_INIT SET_OUTPUT(Y_ENABLE_PIN)
70 #define Y_ENABLE_WRITE(STATE) WRITE(Y_ENABLE_PIN,STATE)
71 #define Y_ENABLE_READ() READ(Y_ENABLE_PIN)
74 #define Y_DIR_INIT SET_OUTPUT(Y_DIR_PIN)
75 #define Y_DIR_WRITE(STATE) WRITE(Y_DIR_PIN,STATE)
76 #define Y_DIR_READ() READ(Y_DIR_PIN)
78 #define Y_STEP_INIT SET_OUTPUT(Y_STEP_PIN)
80 #define Y_STEP_WRITE(STATE) WRITE(Y_STEP_PIN,STATE)
82 #define Y_STEP_READ READ(Y_STEP_PIN)
86 #define Z_ENABLE_INIT SET_OUTPUT(Z_ENABLE_PIN)
87 #define Z_ENABLE_WRITE(STATE) WRITE(Z_ENABLE_PIN,STATE)
88 #define Z_ENABLE_READ() READ(Z_ENABLE_PIN)
91 #define Z_DIR_INIT SET_OUTPUT(Z_DIR_PIN)
92 #define Z_DIR_WRITE(STATE) WRITE(Z_DIR_PIN,STATE)
93 #define Z_DIR_READ() READ(Z_DIR_PIN)
95 #define Z_STEP_INIT SET_OUTPUT(Z_STEP_PIN)
97 #define Z_STEP_WRITE(STATE) WRITE(Z_STEP_PIN,STATE)
99 #define Z_STEP_READ READ(Z_STEP_PIN)
103 #ifndef X2_ENABLE_INIT
104 #define X2_ENABLE_INIT SET_OUTPUT(X2_ENABLE_PIN)
105 #define X2_ENABLE_WRITE(STATE) WRITE(X2_ENABLE_PIN,STATE)
106 #define X2_ENABLE_READ() READ(X2_ENABLE_PIN)
109 #define X2_DIR_INIT SET_OUTPUT(X2_DIR_PIN)
110 #define X2_DIR_WRITE(STATE) WRITE(X2_DIR_PIN,STATE)
111 #define X2_DIR_READ() READ(X2_DIR_PIN)
113 #define X2_STEP_INIT SET_OUTPUT(X2_STEP_PIN)
114 #ifndef X2_STEP_WRITE
115 #define X2_STEP_WRITE(STATE) WRITE(X2_STEP_PIN,STATE)
117 #define X2_STEP_READ READ(X2_STEP_PIN)
122 #ifndef Y2_ENABLE_INIT
123 #define Y2_ENABLE_INIT SET_OUTPUT(Y2_ENABLE_PIN)
124 #define Y2_ENABLE_WRITE(STATE) WRITE(Y2_ENABLE_PIN,STATE)
125 #define Y2_ENABLE_READ() READ(Y2_ENABLE_PIN)
128 #define Y2_DIR_INIT SET_OUTPUT(Y2_DIR_PIN)
129 #define Y2_DIR_WRITE(STATE) WRITE(Y2_DIR_PIN,STATE)
130 #define Y2_DIR_READ() READ(Y2_DIR_PIN)
132 #define Y2_STEP_INIT SET_OUTPUT(Y2_STEP_PIN)
133 #ifndef Y2_STEP_WRITE
134 #define Y2_STEP_WRITE(STATE) WRITE(Y2_STEP_PIN,STATE)
136 #define Y2_STEP_READ READ(Y2_STEP_PIN)
138 #define Y2_DIR_WRITE(STATE) NOOP
143 #ifndef Z2_ENABLE_INIT
144 #define Z2_ENABLE_INIT SET_OUTPUT(Z2_ENABLE_PIN)
145 #define Z2_ENABLE_WRITE(STATE) WRITE(Z2_ENABLE_PIN,STATE)
146 #define Z2_ENABLE_READ() READ(Z2_ENABLE_PIN)
149 #define Z2_DIR_INIT SET_OUTPUT(Z2_DIR_PIN)
150 #define Z2_DIR_WRITE(STATE) WRITE(Z2_DIR_PIN,STATE)
151 #define Z2_DIR_READ() READ(Z2_DIR_PIN)
153 #define Z2_STEP_INIT SET_OUTPUT(Z2_STEP_PIN)
154 #ifndef Z2_STEP_WRITE
155 #define Z2_STEP_WRITE(STATE) WRITE(Z2_STEP_PIN,STATE)
157 #define Z2_STEP_READ READ(Z2_STEP_PIN)
159 #define Z2_DIR_WRITE(STATE) NOOP
164 #ifndef Z3_ENABLE_INIT
165 #define Z3_ENABLE_INIT SET_OUTPUT(Z3_ENABLE_PIN)
166 #define Z3_ENABLE_WRITE(STATE) WRITE(Z3_ENABLE_PIN,STATE)
167 #define Z3_ENABLE_READ() READ(Z3_ENABLE_PIN)
170 #define Z3_DIR_INIT SET_OUTPUT(Z3_DIR_PIN)
171 #define Z3_DIR_WRITE(STATE) WRITE(Z3_DIR_PIN,STATE)
172 #define Z3_DIR_READ() READ(Z3_DIR_PIN)
174 #define Z3_STEP_INIT SET_OUTPUT(Z3_STEP_PIN)
175 #ifndef Z3_STEP_WRITE
176 #define Z3_STEP_WRITE(STATE) WRITE(Z3_STEP_PIN,STATE)
178 #define Z3_STEP_READ READ(Z3_STEP_PIN)
180 #define Z3_DIR_WRITE(STATE) NOOP
184 #ifndef E0_ENABLE_INIT
185 #define E0_ENABLE_INIT SET_OUTPUT(E0_ENABLE_PIN)
186 #define E0_ENABLE_WRITE(STATE) WRITE(E0_ENABLE_PIN,STATE)
187 #define E0_ENABLE_READ() READ(E0_ENABLE_PIN)
190 #define E0_DIR_INIT SET_OUTPUT(E0_DIR_PIN)
191 #define E0_DIR_WRITE(STATE) WRITE(E0_DIR_PIN,STATE)
192 #define E0_DIR_READ() READ(E0_DIR_PIN)
194 #define E0_STEP_INIT SET_OUTPUT(E0_STEP_PIN)
195 #ifndef E0_STEP_WRITE
196 #define E0_STEP_WRITE(STATE) WRITE(E0_STEP_PIN,STATE)
198 #define E0_STEP_READ READ(E0_STEP_PIN)
201 #ifndef E1_ENABLE_INIT
202 #define E1_ENABLE_INIT SET_OUTPUT(E1_ENABLE_PIN)
203 #define E1_ENABLE_WRITE(STATE) WRITE(E1_ENABLE_PIN,STATE)
204 #define E1_ENABLE_READ() READ(E1_ENABLE_PIN)
207 #define E1_DIR_INIT SET_OUTPUT(E1_DIR_PIN)
208 #define E1_DIR_WRITE(STATE) WRITE(E1_DIR_PIN,STATE)
209 #define E1_DIR_READ() READ(E1_DIR_PIN)
211 #define E1_STEP_INIT SET_OUTPUT(E1_STEP_PIN)
212 #ifndef E1_STEP_WRITE
213 #define E1_STEP_WRITE(STATE) WRITE(E1_STEP_PIN,STATE)
215 #define E1_STEP_READ READ(E1_STEP_PIN)
218 #ifndef E2_ENABLE_INIT
219 #define E2_ENABLE_INIT SET_OUTPUT(E2_ENABLE_PIN)
220 #define E2_ENABLE_WRITE(STATE) WRITE(E2_ENABLE_PIN,STATE)
221 #define E2_ENABLE_READ() READ(E2_ENABLE_PIN)
224 #define E2_DIR_INIT SET_OUTPUT(E2_DIR_PIN)
225 #define E2_DIR_WRITE(STATE) WRITE(E2_DIR_PIN,STATE)
226 #define E2_DIR_READ() READ(E2_DIR_PIN)
228 #define E2_STEP_INIT SET_OUTPUT(E2_STEP_PIN)
229 #ifndef E2_STEP_WRITE
230 #define E2_STEP_WRITE(STATE) WRITE(E2_STEP_PIN,STATE)
232 #define E2_STEP_READ READ(E2_STEP_PIN)
235 #ifndef E3_ENABLE_INIT
236 #define E3_ENABLE_INIT SET_OUTPUT(E3_ENABLE_PIN)
237 #define E3_ENABLE_WRITE(STATE) WRITE(E3_ENABLE_PIN,STATE)
238 #define E3_ENABLE_READ() READ(E3_ENABLE_PIN)
241 #define E3_DIR_INIT SET_OUTPUT(E3_DIR_PIN)
242 #define E3_DIR_WRITE(STATE) WRITE(E3_DIR_PIN,STATE)
243 #define E3_DIR_READ() READ(E3_DIR_PIN)
245 #define E3_STEP_INIT SET_OUTPUT(E3_STEP_PIN)
246 #ifndef E3_STEP_WRITE
247 #define E3_STEP_WRITE(STATE) WRITE(E3_STEP_PIN,STATE)
249 #define E3_STEP_READ READ(E3_STEP_PIN)
252 #ifndef E4_ENABLE_INIT
253 #define E4_ENABLE_INIT SET_OUTPUT(E4_ENABLE_PIN)
254 #define E4_ENABLE_WRITE(STATE) WRITE(E4_ENABLE_PIN,STATE)
255 #define E4_ENABLE_READ() READ(E4_ENABLE_PIN)
258 #define E4_DIR_INIT SET_OUTPUT(E4_DIR_PIN)
259 #define E4_DIR_WRITE(STATE) WRITE(E4_DIR_PIN,STATE)
260 #define E4_DIR_READ() READ(E4_DIR_PIN)
262 #define E4_STEP_INIT SET_OUTPUT(E4_STEP_PIN)
263 #ifndef E4_STEP_WRITE
264 #define E4_STEP_WRITE(STATE) WRITE(E4_STEP_PIN,STATE)
266 #define E4_STEP_READ READ(E4_STEP_PIN)
269 #ifndef E5_ENABLE_INIT
270 #define E5_ENABLE_INIT SET_OUTPUT(E5_ENABLE_PIN)
271 #define E5_ENABLE_WRITE(STATE) WRITE(E5_ENABLE_PIN,STATE)
272 #define E5_ENABLE_READ() READ(E5_ENABLE_PIN)
275 #define E5_DIR_INIT SET_OUTPUT(E5_DIR_PIN)
276 #define E5_DIR_WRITE(STATE) WRITE(E5_DIR_PIN,STATE)
277 #define E5_DIR_READ() READ(E5_DIR_PIN)
279 #define E5_STEP_INIT SET_OUTPUT(E5_STEP_PIN)
280 #ifndef E5_STEP_WRITE
281 #define E5_STEP_WRITE(STATE) WRITE(E5_STEP_PIN,STATE)
283 #define E5_STEP_READ READ(E5_STEP_PIN)
288 #if ENABLED(SWITCHING_EXTRUDER) // One stepper driver per two extruders, reversed on odd index
290 #define E_STEP_WRITE(E,V) do{ if (E < 2) { E0_STEP_WRITE(V); } else if (E < 4) { E1_STEP_WRITE(V); } else { E2_STEP_WRITE(V); } }while(0)
291 #define NORM_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 1: E0_DIR_WRITE( INVERT_E0_DIR); break; case 2: E1_DIR_WRITE(!INVERT_E1_DIR); break; case 3: E1_DIR_WRITE( INVERT_E1_DIR); break; case 4: E2_DIR_WRITE(!INVERT_E2_DIR); case 5: E2_DIR_WRITE( INVERT_E2_DIR); } }while(0)
292 #define REV_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE( INVERT_E0_DIR); break; case 1: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 2: E1_DIR_WRITE( INVERT_E1_DIR); break; case 3: E1_DIR_WRITE(!INVERT_E1_DIR); break; case 4: E2_DIR_WRITE( INVERT_E2_DIR); case 5: E2_DIR_WRITE(!INVERT_E2_DIR); } }while(0)
294 #define E_STEP_WRITE(E,V) do{ if (E < 2) { E0_STEP_WRITE(V); } else if (E < 4) { E1_STEP_WRITE(V); } else { E2_STEP_WRITE(V); } }while(0)
295 #define NORM_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 1: E0_DIR_WRITE( INVERT_E0_DIR); break; case 2: E1_DIR_WRITE(!INVERT_E1_DIR); break; case 3: E1_DIR_WRITE( INVERT_E1_DIR); break; case 4: E2_DIR_WRITE(!INVERT_E2_DIR); } }while(0)
296 #define REV_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE( INVERT_E0_DIR); break; case 1: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 2: E1_DIR_WRITE( INVERT_E1_DIR); break; case 3: E1_DIR_WRITE(!INVERT_E1_DIR); break; case 4: E2_DIR_WRITE( INVERT_E2_DIR); } }while(0)
298 #define E_STEP_WRITE(E,V) do{ if (E < 2) { E0_STEP_WRITE(V); } else { E1_STEP_WRITE(V); } }while(0)
299 #define NORM_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 1: E0_DIR_WRITE( INVERT_E0_DIR); break; case 2: E1_DIR_WRITE(!INVERT_E1_DIR); break; case 3: E1_DIR_WRITE( INVERT_E1_DIR); } }while(0)
300 #define REV_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE( INVERT_E0_DIR); break; case 1: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 2: E1_DIR_WRITE( INVERT_E1_DIR); break; case 3: E1_DIR_WRITE(!INVERT_E1_DIR); } }while(0)
302 #define E_STEP_WRITE(E,V) do{ if (E < 2) { E0_STEP_WRITE(V); } else { E1_STEP_WRITE(V); } }while(0)
303 #define NORM_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 1: E0_DIR_WRITE( INVERT_E0_DIR); break; case 2: E1_DIR_WRITE(!INVERT_E1_DIR); } }while(0)
304 #define REV_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE( INVERT_E0_DIR); break; case 1: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 2: E1_DIR_WRITE( INVERT_E1_DIR); } }while(0)
306 #define E_STEP_WRITE(E,V) E0_STEP_WRITE(V)
307 #define NORM_E_DIR(E) do{ E0_DIR_WRITE(E ? INVERT_E0_DIR : !INVERT_E0_DIR); }while(0)
308 #define REV_E_DIR(E) do{ E0_DIR_WRITE(E ? !INVERT_E0_DIR : INVERT_E0_DIR); }while(0)
310 #elif ENABLED(PRUSA_MMU2)
311 #define E_STEP_WRITE(E,V) E0_STEP_WRITE(V)
312 #define NORM_E_DIR(E) E0_DIR_WRITE(!INVERT_E0_DIR)
313 #define REV_E_DIR(E) E0_DIR_WRITE( INVERT_E0_DIR)
315 #elif ENABLED(MK2_MULTIPLEXER) // One multiplexed stepper driver, reversed on odd index
316 #define E_STEP_WRITE(E,V) E0_STEP_WRITE(V)
317 #define NORM_E_DIR(E) do{ E0_DIR_WRITE(TEST(E, 0) ? !INVERT_E0_DIR: INVERT_E0_DIR); }while(0)
318 #define REV_E_DIR(E) do{ E0_DIR_WRITE(TEST(E, 0) ? INVERT_E0_DIR: !INVERT_E0_DIR); }while(0)
323 #define _E_STEP_WRITE(E,V) do{ switch (E) { case 0: E0_STEP_WRITE(V); break; case 1: E1_STEP_WRITE(V); break; case 2: E2_STEP_WRITE(V); break; case 3: E3_STEP_WRITE(V); break; case 4: E4_STEP_WRITE(V); case 5: E5_STEP_WRITE(V); } }while(0)
324 #define _NORM_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 1: E1_DIR_WRITE(!INVERT_E1_DIR); break; case 2: E2_DIR_WRITE(!INVERT_E2_DIR); break; case 3: E3_DIR_WRITE(!INVERT_E3_DIR); break; case 4: E4_DIR_WRITE(!INVERT_E4_DIR); case 5: E5_DIR_WRITE(!INVERT_E5_DIR); } }while(0)
325 #define _REV_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE( INVERT_E0_DIR); break; case 1: E1_DIR_WRITE( INVERT_E1_DIR); break; case 2: E2_DIR_WRITE( INVERT_E2_DIR); break; case 3: E3_DIR_WRITE( INVERT_E3_DIR); break; case 4: E4_DIR_WRITE( INVERT_E4_DIR); case 5: E5_DIR_WRITE( INVERT_E5_DIR); } }while(0)
327 #define _E_STEP_WRITE(E,V) do{ switch (E) { case 0: E0_STEP_WRITE(V); break; case 1: E1_STEP_WRITE(V); break; case 2: E2_STEP_WRITE(V); break; case 3: E3_STEP_WRITE(V); break; case 4: E4_STEP_WRITE(V); } }while(0)
328 #define _NORM_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 1: E1_DIR_WRITE(!INVERT_E1_DIR); break; case 2: E2_DIR_WRITE(!INVERT_E2_DIR); break; case 3: E3_DIR_WRITE(!INVERT_E3_DIR); break; case 4: E4_DIR_WRITE(!INVERT_E4_DIR); } }while(0)
329 #define _REV_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE( INVERT_E0_DIR); break; case 1: E1_DIR_WRITE( INVERT_E1_DIR); break; case 2: E2_DIR_WRITE( INVERT_E2_DIR); break; case 3: E3_DIR_WRITE( INVERT_E3_DIR); break; case 4: E4_DIR_WRITE( INVERT_E4_DIR); } }while(0)
331 #define _E_STEP_WRITE(E,V) do{ switch (E) { case 0: E0_STEP_WRITE(V); break; case 1: E1_STEP_WRITE(V); break; case 2: E2_STEP_WRITE(V); break; case 3: E3_STEP_WRITE(V); } }while(0)
332 #define _NORM_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 1: E1_DIR_WRITE(!INVERT_E1_DIR); break; case 2: E2_DIR_WRITE(!INVERT_E2_DIR); break; case 3: E3_DIR_WRITE(!INVERT_E3_DIR); } }while(0)
333 #define _REV_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE( INVERT_E0_DIR); break; case 1: E1_DIR_WRITE( INVERT_E1_DIR); break; case 2: E2_DIR_WRITE( INVERT_E2_DIR); break; case 3: E3_DIR_WRITE( INVERT_E3_DIR); } }while(0)
335 #define _E_STEP_WRITE(E,V) do{ switch (E) { case 0: E0_STEP_WRITE(V); break; case 1: E1_STEP_WRITE(V); break; case 2: E2_STEP_WRITE(V); } }while(0)
336 #define _NORM_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE(!INVERT_E0_DIR); break; case 1: E1_DIR_WRITE(!INVERT_E1_DIR); break; case 2: E2_DIR_WRITE(!INVERT_E2_DIR); } }while(0)
337 #define _REV_E_DIR(E) do{ switch (E) { case 0: E0_DIR_WRITE( INVERT_E0_DIR); break; case 1: E1_DIR_WRITE( INVERT_E1_DIR); break; case 2: E2_DIR_WRITE( INVERT_E2_DIR); } }while(0)
339 #define _E_STEP_WRITE(E,V) do{ if (E == 0) { E0_STEP_WRITE(V); } else { E1_STEP_WRITE(V); } }while(0)
340 #define _NORM_E_DIR(E) do{ if (E == 0) { E0_DIR_WRITE(!INVERT_E0_DIR); } else { E1_DIR_WRITE(!INVERT_E1_DIR); } }while(0)
341 #define _REV_E_DIR(E) do{ if (E == 0) { E0_DIR_WRITE( INVERT_E0_DIR); } else { E1_DIR_WRITE( INVERT_E1_DIR); } }while(0)
344 #if HAS_DUPLICATION_MODE
346 #if ENABLED(MULTI_NOZZLE_DUPLICATION)
347 #define _DUPE(N,T,V) do{ if (TEST(duplication_e_mask, N)) E##N##_##T##_WRITE(V); }while(0)
349 #define _DUPE(N,T,V) E##N##_##T##_WRITE(V)
352 #define NDIR(N) _DUPE(N,DIR,!INVERT_E##N##_DIR)
353 #define RDIR(N) _DUPE(N,DIR, INVERT_E##N##_DIR)
355 #define E_STEP_WRITE(E,V) do{ if (extruder_duplication_enabled) { DUPE(STEP,V); } else _E_STEP_WRITE(E,V); }while(0)
359 #define DUPE(T,V) do{ _DUPE(0,T,V); _DUPE(1,T,V); _DUPE(2,T,V); _DUPE(3,T,V); _DUPE(4,T,V); _DUPE(5,T,V); }while(0)
360 #define NORM_E_DIR(E) do{ if (extruder_duplication_enabled) { NDIR(0); NDIR(1); NDIR(2); NDIR(3); NDIR(4); NDIR(5); } else _NORM_E_DIR(E); }while(0)
361 #define REV_E_DIR(E) do{ if (extruder_duplication_enabled) { RDIR(0); RDIR(1); RDIR(2); RDIR(3); RDIR(4); RDIR(5); } else _REV_E_DIR(E); }while(0)
363 #define DUPE(T,V) do{ _DUPE(0,T,V); _DUPE(1,T,V); _DUPE(2,T,V); _DUPE(3,T,V); _DUPE(4,T,V); }while(0)
364 #define NORM_E_DIR(E) do{ if (extruder_duplication_enabled) { NDIR(0); NDIR(1); NDIR(2); NDIR(3); NDIR(4); } else _NORM_E_DIR(E); }while(0)
365 #define REV_E_DIR(E) do{ if (extruder_duplication_enabled) { RDIR(0); RDIR(1); RDIR(2); RDIR(3); RDIR(4); } else _REV_E_DIR(E); }while(0)
367 #define DUPE(T,V) do{ _DUPE(0,T,V); _DUPE(1,T,V); _DUPE(2,T,V); _DUPE(3,T,V); }while(0)
368 #define NORM_E_DIR(E) do{ if (extruder_duplication_enabled) { NDIR(0); NDIR(1); NDIR(2); NDIR(3); } else _NORM_E_DIR(E); }while(0)
369 #define REV_E_DIR(E) do{ if (extruder_duplication_enabled) { RDIR(0); RDIR(1); RDIR(2); RDIR(3); } else _REV_E_DIR(E); }while(0)
371 #define DUPE(T,V) do{ _DUPE(0,T,V); _DUPE(1,T,V); _DUPE(2,T,V); }while(0)
372 #define NORM_E_DIR(E) do{ if (extruder_duplication_enabled) { NDIR(0); NDIR(1); NDIR(2); } else _NORM_E_DIR(E); }while(0)
373 #define REV_E_DIR(E) do{ if (extruder_duplication_enabled) { RDIR(0); RDIR(1); RDIR(2); } else _REV_E_DIR(E); }while(0)
376 #define DUPE(T,V) do{ _DUPE(0,T,V); _DUPE(1,T,V); }while(0)
377 #define NORM_E_DIR(E) do{ if (extruder_duplication_enabled) { NDIR(0); NDIR(1); } else _NORM_E_DIR(E); }while(0)
378 #define REV_E_DIR(E) do{ if (extruder_duplication_enabled) { RDIR(0); RDIR(1); } else _REV_E_DIR(E); }while(0)
383 #define E_STEP_WRITE(E,V) _E_STEP_WRITE(E,V)
384 #define NORM_E_DIR(E) _NORM_E_DIR(E)
385 #define REV_E_DIR(E) _REV_E_DIR(E)
390 #define E_STEP_WRITE(E,V) E0_STEP_WRITE(V)
391 #define NORM_E_DIR(E) E0_DIR_WRITE(!INVERT_E0_DIR)
392 #define REV_E_DIR(E) E0_DIR_WRITE( INVERT_E0_DIR)
395 #define E_STEP_WRITE(E,V) NOOP
396 #define NORM_E_DIR(E) NOOP
397 #define REV_E_DIR(E) NOOP
void reset_stepper_drivers()
Definition: indirection.cpp:41
static void init_to_defaults()
void tmc26x_init_to_defaults()
void reset_stepper_drivers()
Definition: indirection.cpp:41
void restore_trinamic_drivers()
void restore_stepper_drivers()
Definition: indirection.cpp:35
void restore_stepper_drivers()
Definition: indirection.cpp:35
void reset_trinamic_drivers()