port.c File Reference

#include "FreeRTOS.h"
#include "task.h"

Macros
#define	configSYSTICK_CLOCK_HZ   configCPU_CLOCK_HZ
#define	portNVIC_SYSTICK_CLK_BIT   ( 1UL << 2UL )
#define	portNVIC_SYSTICK_CTRL_REG   ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
#define	portNVIC_SYSTICK_LOAD_REG   ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
#define	portNVIC_SYSTICK_CURRENT_VALUE_REG   ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
#define	portNVIC_SYSPRI2_REG   ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
#define	portNVIC_SYSTICK_INT_BIT   ( 1UL << 1UL )
#define	portNVIC_SYSTICK_ENABLE_BIT   ( 1UL << 0UL )
#define	portNVIC_SYSTICK_COUNT_FLAG_BIT   ( 1UL << 16UL )
#define	portNVIC_PENDSVCLEAR_BIT   ( 1UL << 27UL )
#define	portNVIC_PEND_SYSTICK_CLEAR_BIT   ( 1UL << 25UL )
#define	portCPUID   ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
#define	portCORTEX_M7_r0p1_ID   ( 0x410FC271UL )
#define	portCORTEX_M7_r0p0_ID   ( 0x410FC270UL )
#define	portNVIC_PENDSV_PRI   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
#define	portNVIC_SYSTICK_PRI   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
#define	portFIRST_USER_INTERRUPT_NUMBER   ( 16 )
#define	portNVIC_IP_REGISTERS_OFFSET_16   ( 0xE000E3F0 )
#define	portAIRCR_REG   ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
#define	portMAX_8_BIT_VALUE   ( ( uint8_t ) 0xff )
#define	portTOP_BIT_OF_BYTE   ( ( uint8_t ) 0x80 )
#define	portMAX_PRIGROUP_BITS   ( ( uint8_t ) 7 )
#define	portPRIORITY_GROUP_MASK   ( 0x07UL << 8UL )
#define	portPRIGROUP_SHIFT   ( 8UL )
#define	portVECTACTIVE_MASK   ( 0xFFUL )
#define	portFPCCR   ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
#define	portASPEN_AND_LSPEN_BITS   ( 0x3UL << 30UL )
#define	portINITIAL_XPSR   ( 0x01000000 )
#define	portINITIAL_EXEC_RETURN   ( 0xfffffffd )
#define	portMAX_24_BIT_NUMBER   ( 0xffffffUL )
#define	portSTART_ADDRESS_MASK   ( ( StackType_t ) 0xfffffffeUL )
#define	portMISSED_COUNTS_FACTOR   ( 45UL )
#define	portTASK_RETURN_ADDRESS   prvTaskExitError

Functions
void	vPortSetupTimerInterrupt (void)
void	xPortPendSVHandler (void xPortSysTickHandler void)
static void	prvTaskExitError (void)
void	vPortSVCHandler (void)
static void	prvPortStartFirstTask (void)
BaseType_t	xPortStartScheduler (void)
void	vPortEndScheduler (void)
void	vPortEnterCritical (void)
void	vPortExitCritical (void)
void	xPortPendSVHandler (void)
void	xPortSysTickHandler (void)
	__attribute__ ((weak))
static void	vPortEnableVFP (void)

Variables
static UBaseType_t	uxCriticalNesting = 0xaaaaaaaa

Macro Definition Documentation

configSYSTICK_CLOCK_HZ

#define configSYSTICK_CLOCK_HZ   configCPU_CLOCK_HZ

portNVIC_SYSTICK_CLK_BIT

#define portNVIC_SYSTICK_CLK_BIT   ( 1UL << 2UL )

portNVIC_SYSTICK_CTRL_REG

#define portNVIC_SYSTICK_CTRL_REG   ( * ( ( volatile uint32_t * ) 0xe000e010 ) )

portNVIC_SYSTICK_LOAD_REG

#define portNVIC_SYSTICK_LOAD_REG   ( * ( ( volatile uint32_t * ) 0xe000e014 ) )

portNVIC_SYSTICK_CURRENT_VALUE_REG

#define portNVIC_SYSTICK_CURRENT_VALUE_REG   ( * ( ( volatile uint32_t * ) 0xe000e018 ) )

portNVIC_SYSPRI2_REG

#define portNVIC_SYSPRI2_REG   ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )

portNVIC_SYSTICK_INT_BIT

#define portNVIC_SYSTICK_INT_BIT   ( 1UL << 1UL )

portNVIC_SYSTICK_ENABLE_BIT

#define portNVIC_SYSTICK_ENABLE_BIT   ( 1UL << 0UL )

portNVIC_SYSTICK_COUNT_FLAG_BIT

#define portNVIC_SYSTICK_COUNT_FLAG_BIT   ( 1UL << 16UL )

portNVIC_PENDSVCLEAR_BIT

#define portNVIC_PENDSVCLEAR_BIT   ( 1UL << 27UL )

portNVIC_PEND_SYSTICK_CLEAR_BIT

#define portNVIC_PEND_SYSTICK_CLEAR_BIT   ( 1UL << 25UL )

portCPUID

#define portCPUID   ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )

portCORTEX_M7_r0p1_ID

#define portCORTEX_M7_r0p1_ID   ( 0x410FC271UL )

portCORTEX_M7_r0p0_ID

#define portCORTEX_M7_r0p0_ID   ( 0x410FC270UL )

portNVIC_PENDSV_PRI

#define portNVIC_PENDSV_PRI   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )

portNVIC_SYSTICK_PRI

#define portNVIC_SYSTICK_PRI   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )

portFIRST_USER_INTERRUPT_NUMBER

#define portFIRST_USER_INTERRUPT_NUMBER   ( 16 )

portNVIC_IP_REGISTERS_OFFSET_16

#define portNVIC_IP_REGISTERS_OFFSET_16   ( 0xE000E3F0 )

portAIRCR_REG

#define portAIRCR_REG   ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )

portMAX_8_BIT_VALUE

#define portMAX_8_BIT_VALUE   ( ( uint8_t ) 0xff )

portTOP_BIT_OF_BYTE

#define portTOP_BIT_OF_BYTE   ( ( uint8_t ) 0x80 )

portMAX_PRIGROUP_BITS

#define portMAX_PRIGROUP_BITS   ( ( uint8_t ) 7 )

portPRIORITY_GROUP_MASK

#define portPRIORITY_GROUP_MASK   ( 0x07UL << 8UL )

portPRIGROUP_SHIFT

#define portPRIGROUP_SHIFT   ( 8UL )

portVECTACTIVE_MASK

#define portVECTACTIVE_MASK   ( 0xFFUL )

portFPCCR

#define portFPCCR   ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */

portASPEN_AND_LSPEN_BITS

#define portASPEN_AND_LSPEN_BITS   ( 0x3UL << 30UL )

portINITIAL_XPSR

#define portINITIAL_XPSR   ( 0x01000000 )

portINITIAL_EXEC_RETURN

#define portINITIAL_EXEC_RETURN   ( 0xfffffffd )

portMAX_24_BIT_NUMBER

#define portMAX_24_BIT_NUMBER   ( 0xffffffUL )

portSTART_ADDRESS_MASK

#define portSTART_ADDRESS_MASK   ( ( StackType_t ) 0xfffffffeUL )

portMISSED_COUNTS_FACTOR

#define portMISSED_COUNTS_FACTOR   ( 45UL )

portTASK_RETURN_ADDRESS

#define portTASK_RETURN_ADDRESS   prvTaskExitError

Function Documentation

vPortSetupTimerInterrupt()

void vPortSetupTimerInterrupt

(

void

)

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xPortPendSVHandler() [1/2]

void xPortPendSVHandler

(

void xPortSysTickHandler

void

)

{
    /* Simulate the stack frame as it would be created by a context switch
    interrupt. */
 
    /* Offset added to account for the way the MCU uses the stack on entry/exit
    of interrupts, and to ensure alignment. */
    pxTopOfStack--;
 
    *pxTopOfStack = portINITIAL_XPSR;   /* xPSR */
    pxTopOfStack--;
    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */
    pxTopOfStack--;
    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;    /* LR */
 
    /* Save code space by skipping register initialisation. */
    pxTopOfStack -= 5;  /* R12, R3, R2 and R1. */
    *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */
 
    /* A save method is being used that requires each task to maintain its
    own exec return value. */
    pxTopOfStack--;
    *pxTopOfStack = portINITIAL_EXEC_RETURN;
 
    pxTopOfStack -= 8;  /* R11, R10, R9, R8, R7, R6, R5 and R4. */
 
    return pxTopOfStack;
}

prvTaskExitError()

static void prvTaskExitError ( void  )

static

{
    /* A function that implements a task must not exit or attempt to return to
    its caller as there is nothing to return to.  If a task wants to exit it
    should instead call vTaskDelete( NULL ).
 
    Artificially force an assert() to be triggered if configASSERT() is
    defined, then stop here so application writers can catch the error. */
    configASSERT( uxCriticalNesting == ~0UL );
    portDISABLE_INTERRUPTS();
    for( ;; );
}

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vPortSVCHandler()

void vPortSVCHandler

(

void

)

{
    __asm volatile (
                    "   ldr r3, pxCurrentTCBConst2      \n" /* Restore the context. */
                    "   ldr r1, [r3]                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
                    "   ldr r0, [r1]                    \n" /* The first item in pxCurrentTCB is the task top of stack. */
                    "   ldmia r0!, {r4-r11, r14}        \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
                    "   msr psp, r0                     \n" /* Restore the task stack pointer. */
                    "   isb                             \n"
                    "   mov r0, #0                      \n"
                    "   msr basepri, r0                 \n"
                    "   bx r14                          \n"
                    "                                   \n"
                    "   .align 4                        \n"
                    "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
                );
}

prvPortStartFirstTask()

static void prvPortStartFirstTask ( void  )

static

{
    __asm volatile(
                    " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */
                    " ldr r0, [r0]          \n"
                    " ldr r0, [r0]          \n"
                    " msr msp, r0           \n" /* Set the msp back to the start of the stack. */
                    " cpsie i               \n" /* Globally enable interrupts. */
                    " cpsie f               \n"
                    " dsb                   \n"
                    " isb                   \n"
                    " svc 0                 \n" /* System call to start first task. */
                    " nop                   \n"
                );
}

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xPortStartScheduler()

BaseType_t xPortStartScheduler

(

void

)

{
    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
    See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
 
    /* This port can be used on all revisions of the Cortex-M7 core other than
    the r0p1 parts.  r0p1 parts should use the port from the
    /source/portable/GCC/ARM_CM7/r0p1 directory. */
    configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
    configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
 
    #if( configASSERT_DEFINED == 1 )
    {
        volatile uint32_t ulOriginalPriority;
        volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
        volatile uint8_t ucMaxPriorityValue;
 
        /* Determine the maximum priority from which ISR safe FreeRTOS API
        functions can be called.  ISR safe functions are those that end in
        "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
        ensure interrupt entry is as fast and simple as possible.
 
        Save the interrupt priority value that is about to be clobbered. */
        ulOriginalPriority = *pucFirstUserPriorityRegister;
 
        /* Determine the number of priority bits available.  First write to all
        possible bits. */
        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
 
        /* Read the value back to see how many bits stuck. */
        ucMaxPriorityValue = *pucFirstUserPriorityRegister;
 
        /* Use the same mask on the maximum system call priority. */
        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 
        /* Calculate the maximum acceptable priority group value for the number
        of bits read back. */
        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
        {
            ulMaxPRIGROUPValue--;
            ucMaxPriorityValue <<= ( uint8_t ) 0x01;
        }
 
        /* Shift the priority group value back to its position within the AIRCR
        register. */
        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
 
        /* Restore the clobbered interrupt priority register to its original
        value. */
        *pucFirstUserPriorityRegister = ulOriginalPriority;
    }
    #endif /* conifgASSERT_DEFINED */
 
    /* Make PendSV and SysTick the lowest priority interrupts. */
    portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
    portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
 
    /* Start the timer that generates the tick ISR.  Interrupts are disabled
    here already. */
    vPortSetupTimerInterrupt();
 
    /* Initialise the critical nesting count ready for the first task. */
    uxCriticalNesting = 0;
 
    /* Ensure the VFP is enabled - it should be anyway. */
    vPortEnableVFP();
 
    /* Lazy save always. */
    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
 
    /* Start the first task. */
    prvPortStartFirstTask();
 
    /* Should never get here as the tasks will now be executing!  Call the task
    exit error function to prevent compiler warnings about a static function
    not being called in the case that the application writer overrides this
    functionality by defining configTASK_RETURN_ADDRESS. */
    prvTaskExitError();
 
    /* Should not get here! */
    return 0;
}

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vPortEndScheduler()

void vPortEndScheduler

(

void

)

{
    /* Not implemented in ports where there is nothing to return to.
    Artificially force an assert. */
    configASSERT( uxCriticalNesting == 1000UL );
}

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vPortEnterCritical()

void vPortEnterCritical

(

void

)

{
    portDISABLE_INTERRUPTS();
    uxCriticalNesting++;
 
    /* This is not the interrupt safe version of the enter critical function so
    assert() if it is being called from an interrupt context.  Only API
    functions that end in "FromISR" can be used in an interrupt.  Only assert if
    the critical nesting count is 1 to protect against recursive calls if the
    assert function also uses a critical section. */
    if( uxCriticalNesting == 1 )
    {
        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
    }
}

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vPortExitCritical()

void vPortExitCritical

(

void

)

{
    configASSERT( uxCriticalNesting );
    uxCriticalNesting--;
    if( uxCriticalNesting == 0 )
    {
        portENABLE_INTERRUPTS();
    }
}

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xPortPendSVHandler() [2/2]

void xPortPendSVHandler

(

void

)

{
    /* This is a naked function. */
 
    __asm volatile
    (
    "   mrs r0, psp                         \n"
    "   isb                                 \n"
    "                                       \n"
    "   ldr r3, pxCurrentTCBConst           \n" /* Get the location of the current TCB. */
    "   ldr r2, [r3]                        \n"
    "                                       \n"
    "   tst r14, #0x10                      \n" /* Is the task using the FPU context?  If so, push high vfp registers. */
    "   it eq                               \n"
    "   vstmdbeq r0!, {s16-s31}             \n"
    "                                       \n"
    "   stmdb r0!, {r4-r11, r14}            \n" /* Save the core registers. */
    "                                       \n"
    "   str r0, [r2]                        \n" /* Save the new top of stack into the first member of the TCB. */
    "                                       \n"
    "   stmdb sp!, {r3}                     \n"
    "   mov r0, %0                          \n"
    "   msr basepri, r0                     \n"
    "   dsb                                 \n"
    "   isb                                 \n"
    "   bl vTaskSwitchContext               \n"
    "   mov r0, #0                          \n"
    "   msr basepri, r0                     \n"
    "   ldmia sp!, {r3}                     \n"
    "                                       \n"
    "   ldr r1, [r3]                        \n" /* The first item in pxCurrentTCB is the task top of stack. */
    "   ldr r0, [r1]                        \n"
    "                                       \n"
    "   ldmia r0!, {r4-r11, r14}            \n" /* Pop the core registers. */
    "                                       \n"
    "   tst r14, #0x10                      \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
    "   it eq                               \n"
    "   vldmiaeq r0!, {s16-s31}             \n"
    "                                       \n"
    "   msr psp, r0                         \n"
    "   isb                                 \n"
    "                                       \n"
    #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
        #if WORKAROUND_PMU_CM001 == 1
    "           push { r14 }                \n"
    "           pop { pc }                  \n"
        #endif
    #endif
    "                                       \n"
    "   bx r14                              \n"
    "                                       \n"
    "   .align 4                            \n"
    "pxCurrentTCBConst: .word pxCurrentTCB  \n"
    ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
    );
}

xPortSysTickHandler()

void xPortSysTickHandler

(

void

)

{
    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
    executes all interrupts must be unmasked.  There is therefore no need to
    save and then restore the interrupt mask value as its value is already
    known. */
    portDISABLE_INTERRUPTS();
    {
        /* Increment the RTOS tick. */
        if( xTaskIncrementTick() != pdFALSE )
        {
            /* A context switch is required.  Context switching is performed in
            the PendSV interrupt.  Pend the PendSV interrupt. */
            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
        }
    }
    portENABLE_INTERRUPTS();
}

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__attribute__()

__attribute__

(

(weak)

)

{
    /* Calculate the constants required to configure the tick interrupt. */
    #if configUSE_TICKLESS_IDLE == 1
    {
        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
    }
    #endif /* configUSE_TICKLESS_IDLE */
 
    /* Configure SysTick to interrupt at the requested rate. */
    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}

vPortEnableVFP()

static void vPortEnableVFP ( void  )

static

{
    __asm volatile
    (
        "   ldr.w r0, =0xE000ED88       \n" /* The FPU enable bits are in the CPACR. */
        "   ldr r1, [r0]                \n"
        "                               \n"
        "   orr r1, r1, #( 0xf << 20 )  \n" /* Enable CP10 and CP11 coprocessors, then save back. */
        "   str r1, [r0]                \n"
        "   bx r14                      "
    );
}

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Variable Documentation

uxCriticalNesting

UBaseType_t uxCriticalNesting = 0xaaaaaaaa

static