TIM Exported Types

Collaboration diagram for TIM Exported Types:

Classes
struct	TIM_Base_InitTypeDef
	TIM Time base Configuration Structure definition. More...
struct	TIM_OC_InitTypeDef
	TIM Output Compare Configuration Structure definition. More...
struct	TIM_OnePulse_InitTypeDef
	TIM One Pulse Mode Configuration Structure definition. More...
struct	TIM_IC_InitTypeDef
	TIM Input Capture Configuration Structure definition. More...
struct	TIM_Encoder_InitTypeDef
	TIM Encoder Configuration Structure definition. More...
struct	TIM_ClockConfigTypeDef
	Clock Configuration Handle Structure definition. More...
struct	TIM_ClearInputConfigTypeDef
	Clear Input Configuration Handle Structure definition. More...
struct	TIM_SlaveConfigTypeDef
	TIM Slave configuration Structure definition. More...
struct	TIM_HandleTypeDef
	TIM Time Base Handle Structure definition. More...

Enumerations
enum	HAL_TIM_StateTypeDef {   HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,   HAL_TIM_STATE_ERROR = 0x04U }
	HAL State structures definition. More...
enum	HAL_TIM_ActiveChannel {   HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,   HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U }
	HAL Active channel structures definition. More...

Detailed Description

Enumeration Type Documentation

HAL_TIM_StateTypeDef

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing

{
  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
}HAL_TIM_StateTypeDef;

HAL_TIM_ActiveChannel

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared

{
  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
}HAL_TIM_ActiveChannel;