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stm32f4xx_hal_rcc_ex.h
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1 /**
2  ******************************************************************************
3  * @file stm32f4xx_hal_rcc_ex.h
4  * @author MCD Application Team
5  * @brief Header file of RCC HAL Extension module.
6  ******************************************************************************
7  * @attention
8  *
9  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10  *
11  * Redistribution and use in source and binary forms, with or without modification,
12  * are permitted provided that the following conditions are met:
13  * 1. Redistributions of source code must retain the above copyright notice,
14  * this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright notice,
16  * this list of conditions and the following disclaimer in the documentation
17  * and/or other materials provided with the distribution.
18  * 3. Neither the name of STMicroelectronics nor the names of its contributors
19  * may be used to endorse or promote products derived from this software
20  * without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  ******************************************************************************
34  */
35 
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_HAL_RCC_EX_H
38 #define __STM32F4xx_HAL_RCC_EX_H
39 
40 #ifdef __cplusplus
41  extern "C" {
42 #endif
43 
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f4xx_hal_def.h"
46 
47 /** @addtogroup STM32F4xx_HAL_Driver
48  * @{
49  */
50 
51 /** @addtogroup RCCEx
52  * @{
53  */
54 
55 /* Exported types ------------------------------------------------------------*/
56 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
57  * @{
58  */
59 
60 /**
61  * @brief RCC PLL configuration structure definition
62  */
63 typedef struct
64 {
65  uint32_t PLLState; /*!< The new state of the PLL.
66  This parameter can be a value of @ref RCC_PLL_Config */
67 
68  uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
69  This parameter must be a value of @ref RCC_PLL_Clock_Source */
70 
71  uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
72  This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
73 
74  uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
75  This parameter must be a number between Min_Data = 50 and Max_Data = 432
76  except for STM32F411xE devices where the Min_Data = 192 */
77 
78  uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
79  This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
80 
81  uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
82  This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
83 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
84  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
85  defined(STM32F413xx) || defined(STM32F423xx)
86  uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
87  This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
88  and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
89  This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
90 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
91 }RCC_PLLInitTypeDef;
92 
93 #if defined(STM32F446xx)
94 /**
95  * @brief PLLI2S Clock structure definition
96  */
97 typedef struct
98 {
99  uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
100  This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
101 
102  uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
103  This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
104 
105  uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
106  This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
107 
108  uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
109  This parameter must be a number between Min_Data = 2 and Max_Data = 15.
110  This parameter will be used only when PLLI2S is selected as Clock Source SAI */
111 
112  uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
113  This parameter must be a number between Min_Data = 2 and Max_Data = 7.
114  This parameter will be used only when PLLI2S is selected as Clock Source I2S */
115 }RCC_PLLI2SInitTypeDef;
116 
117 /**
118  * @brief PLLSAI Clock structure definition
119  */
120 typedef struct
121 {
122  uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
123  This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
124 
125  uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
126  This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
127 
128  uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
129  This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
130 
131  uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
132  This parameter must be a number between Min_Data = 2 and Max_Data = 15.
133  This parameter will be used only when PLLSAI is selected as Clock Source SAI */
134 }RCC_PLLSAIInitTypeDef;
135 
136 /**
137  * @brief RCC extended clocks structure definition
138  */
139 typedef struct
140 {
141  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
142  This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
143 
144  RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
145  This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
146 
147  RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
148  This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
149 
150  uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
151  This parameter must be a number between Min_Data = 1 and Max_Data = 32
152  This parameter will be used only when PLLI2S is selected as Clock Source SAI */
153 
154  uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
155  This parameter must be a number between Min_Data = 1 and Max_Data = 32
156  This parameter will be used only when PLLSAI is selected as Clock Source SAI */
157 
158  uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
159  This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
160 
161  uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
162  This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
163 
164  uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
165  This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
166 
167  uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
168  This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
169 
170  uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
171  This parameter can be a value of @ref RCC_RTC_Clock_Source */
172 
173  uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
174  This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
175 
176  uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
177  This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
178 
179  uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
180  This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
181 
182  uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
183  This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
184 
185  uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
186  This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
187 
188  uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
189  This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
190 }RCC_PeriphCLKInitTypeDef;
191 #endif /* STM32F446xx */
192 
193 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
194 /**
195  * @brief RCC extended clocks structure definition
196  */
197 typedef struct
198 {
199  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
200  This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
201 
202  uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
203  This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
204 
205  uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
206  This parameter can be a value of @ref RCC_RTC_Clock_Source */
207 
208  uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
209  This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
210 
211  uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
212  This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
213 
214  uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
215  This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
216 }RCC_PeriphCLKInitTypeDef;
217 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
218 
219 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
220 /**
221  * @brief PLLI2S Clock structure definition
222  */
223 typedef struct
224 {
225  uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
226  This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
227 
228  uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
229  This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
230 
231  uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
232  This parameter must be a number between Min_Data = 2 and Max_Data = 15.
233  This parameter will be used only when PLLI2S is selected as Clock Source SAI */
234 
235  uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
236  This parameter must be a number between Min_Data = 2 and Max_Data = 7.
237  This parameter will be used only when PLLI2S is selected as Clock Source I2S */
238 }RCC_PLLI2SInitTypeDef;
239 
240 /**
241  * @brief RCC extended clocks structure definition
242  */
243 typedef struct
244 {
245  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
246  This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
247 
248  RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
249  This parameter will be used only when PLLI2S is selected as Clock Source I2S */
250 
251 #if defined(STM32F413xx) || defined(STM32F423xx)
252  uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock.
253  This parameter must be a number between Min_Data = 1 and Max_Data = 32
254  This parameter will be used only when PLL is selected as Clock Source SAI */
255 
256  uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock.
257  This parameter must be a number between Min_Data = 1 and Max_Data = 32
258  This parameter will be used only when PLLI2S is selected as Clock Source SAI */
259 #endif /* STM32F413xx || STM32F423xx */
260 
261  uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
262  This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
263 
264  uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
265  This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
266 
267  uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
268  This parameter can be a value of @ref RCC_RTC_Clock_Source */
269 
270  uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
271  This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
272 
273  uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
274  This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
275 
276  uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
277  This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
278 
279  uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection.
280  This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
281 
282  uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
283  This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
284 
285 #if defined(STM32F413xx) || defined(STM32F423xx)
286  uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection.
287  This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
288 
289  uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
290  This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
291 
292  uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
293  This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
294 
295  uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection
296  This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
297 
298  uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection
299  This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
300 #endif /* STM32F413xx || STM32F423xx */
301 
302  uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection.
303  This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
304 
305  uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
306  This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
307 }RCC_PeriphCLKInitTypeDef;
308 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
309 
310 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
311 
312 /**
313  * @brief PLLI2S Clock structure definition
314  */
315 typedef struct
316 {
317  uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
318  This parameter must be a number between Min_Data = 50 and Max_Data = 432.
319  This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
320 
321  uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
322  This parameter must be a number between Min_Data = 2 and Max_Data = 7.
323  This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
324 
325  uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
326  This parameter must be a number between Min_Data = 2 and Max_Data = 15.
327  This parameter will be used only when PLLI2S is selected as Clock Source SAI */
328 }RCC_PLLI2SInitTypeDef;
329 
330 /**
331  * @brief PLLSAI Clock structure definition
332  */
333 typedef struct
334 {
335  uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
336  This parameter must be a number between Min_Data = 50 and Max_Data = 432.
337  This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
338 #if defined(STM32F469xx) || defined(STM32F479xx)
339  uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
340  This parameter is only available in STM32F469xx/STM32F479xx devices.
341  This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
342 #endif /* STM32F469xx || STM32F479xx */
343 
344  uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
345  This parameter must be a number between Min_Data = 2 and Max_Data = 15.
346  This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
347 
348  uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
349  This parameter must be a number between Min_Data = 2 and Max_Data = 7.
350  This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
351 
352 }RCC_PLLSAIInitTypeDef;
353 
354 /**
355  * @brief RCC extended clocks structure definition
356  */
357 typedef struct
358 {
359  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
360  This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
361 
362  RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
363  This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
364 
365  RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
366  This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
367 
368  uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
369  This parameter must be a number between Min_Data = 1 and Max_Data = 32
370  This parameter will be used only when PLLI2S is selected as Clock Source SAI */
371 
372  uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
373  This parameter must be a number between Min_Data = 1 and Max_Data = 32
374  This parameter will be used only when PLLSAI is selected as Clock Source SAI */
375 
376  uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
377  This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
378 
379  uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
380  This parameter can be a value of @ref RCC_RTC_Clock_Source */
381 
382  uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
383  This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
384 #if defined(STM32F469xx) || defined(STM32F479xx)
385  uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
386  This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
387 
388  uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
389  This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
390 #endif /* STM32F469xx || STM32F479xx */
391 }RCC_PeriphCLKInitTypeDef;
392 
393 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
394 
395 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
396  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
397 /**
398  * @brief PLLI2S Clock structure definition
399  */
400 typedef struct
401 {
402 #if defined(STM32F411xE)
403  uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
404  This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
405 #endif /* STM32F411xE */
406 
407  uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
408  This parameter must be a number between Min_Data = 50 and Max_Data = 432
409  Except for STM32F411xE devices where the Min_Data = 192.
410  This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
411 
412  uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
413  This parameter must be a number between Min_Data = 2 and Max_Data = 7.
414  This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
415 
416 }RCC_PLLI2SInitTypeDef;
417 
418 /**
419  * @brief RCC extended clocks structure definition
420  */
421 typedef struct
422 {
423  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
424  This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
425 
426  RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
427  This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
428 
429  uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
430  This parameter can be a value of @ref RCC_RTC_Clock_Source */
431 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
432  uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
433  This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
434 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
435 }RCC_PeriphCLKInitTypeDef;
436 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
437 /**
438  * @}
439  */
440 
441 /* Exported constants --------------------------------------------------------*/
442 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
443  * @{
444  */
445 
446 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
447  * @{
448  */
449 /* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
450 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
451  defined(STM32F413xx) || defined(STM32F423xx)
452 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U
453 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U
454 #define RCC_PERIPHCLK_TIM 0x00000004U
455 #define RCC_PERIPHCLK_RTC 0x00000008U
456 #define RCC_PERIPHCLK_FMPI2C1 0x00000010U
457 #define RCC_PERIPHCLK_CLK48 0x00000020U
458 #define RCC_PERIPHCLK_SDIO 0x00000040U
459 #define RCC_PERIPHCLK_PLLI2S 0x00000080U
460 #define RCC_PERIPHCLK_DFSDM1 0x00000100U
461 #define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U
462 #endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */
463 #if defined(STM32F413xx) || defined(STM32F423xx)
464 #define RCC_PERIPHCLK_DFSDM2 0x00000400U
465 #define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U
466 #define RCC_PERIPHCLK_LPTIM1 0x00001000U
467 #define RCC_PERIPHCLK_SAIA 0x00002000U
468 #define RCC_PERIPHCLK_SAIB 0x00004000U
469 #endif /* STM32F413xx || STM32F423xx */
470 /*----------------------------------------------------------------------------*/
471 
472 /*------------------- Peripheral Clock source for STM32F410xx ----------------*/
473 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
474 #define RCC_PERIPHCLK_I2S 0x00000001U
475 #define RCC_PERIPHCLK_TIM 0x00000002U
476 #define RCC_PERIPHCLK_RTC 0x00000004U
477 #define RCC_PERIPHCLK_FMPI2C1 0x00000008U
478 #define RCC_PERIPHCLK_LPTIM1 0x00000010U
479 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
480 /*----------------------------------------------------------------------------*/
481 
482 /*------------------- Peripheral Clock source for STM32F446xx ----------------*/
483 #if defined(STM32F446xx)
484 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U
485 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U
486 #define RCC_PERIPHCLK_SAI1 0x00000004U
487 #define RCC_PERIPHCLK_SAI2 0x00000008U
488 #define RCC_PERIPHCLK_TIM 0x00000010U
489 #define RCC_PERIPHCLK_RTC 0x00000020U
490 #define RCC_PERIPHCLK_CEC 0x00000040U
491 #define RCC_PERIPHCLK_FMPI2C1 0x00000080U
492 #define RCC_PERIPHCLK_CLK48 0x00000100U
493 #define RCC_PERIPHCLK_SDIO 0x00000200U
494 #define RCC_PERIPHCLK_SPDIFRX 0x00000400U
495 #define RCC_PERIPHCLK_PLLI2S 0x00000800U
496 #endif /* STM32F446xx */
497 /*-----------------------------------------------------------------------------*/
498 
499 /*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/
500 #if defined(STM32F469xx) || defined(STM32F479xx)
501 #define RCC_PERIPHCLK_I2S 0x00000001U
502 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
503 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
504 #define RCC_PERIPHCLK_LTDC 0x00000008U
505 #define RCC_PERIPHCLK_TIM 0x00000010U
506 #define RCC_PERIPHCLK_RTC 0x00000020U
507 #define RCC_PERIPHCLK_PLLI2S 0x00000040U
508 #define RCC_PERIPHCLK_CLK48 0x00000080U
509 #define RCC_PERIPHCLK_SDIO 0x00000100U
510 #endif /* STM32F469xx || STM32F479xx */
511 /*----------------------------------------------------------------------------*/
512 
513 /*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/
514 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
515 #define RCC_PERIPHCLK_I2S 0x00000001U
516 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
517 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
518 #define RCC_PERIPHCLK_LTDC 0x00000008U
519 #define RCC_PERIPHCLK_TIM 0x00000010U
520 #define RCC_PERIPHCLK_RTC 0x00000020U
521 #define RCC_PERIPHCLK_PLLI2S 0x00000040U
522 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
523 /*----------------------------------------------------------------------------*/
524 
525 /*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/
526 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
527  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
528 #define RCC_PERIPHCLK_I2S 0x00000001U
529 #define RCC_PERIPHCLK_RTC 0x00000002U
530 #define RCC_PERIPHCLK_PLLI2S 0x00000004U
531 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
532 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
533 #define RCC_PERIPHCLK_TIM 0x00000008U
534 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
535 /*----------------------------------------------------------------------------*/
536 /**
537  * @}
538  */
539 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
540  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
541  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
542  defined(STM32F479xx)
543 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
544  * @{
545  */
546 #define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U
547 #define RCC_I2SCLKSOURCE_EXT 0x00000001U
548 /**
549  * @}
550  */
551 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
552  STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
553 
554 /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
555  * @{
556  */
557 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
558  defined(STM32F469xx) || defined(STM32F479xx)
559 #define RCC_PLLSAIDIVR_2 0x00000000U
560 #define RCC_PLLSAIDIVR_4 0x00010000U
561 #define RCC_PLLSAIDIVR_8 0x00020000U
562 #define RCC_PLLSAIDIVR_16 0x00030000U
563 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
564 /**
565  * @}
566  */
567 
568 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
569  * @{
570  */
571 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
572  defined(STM32F412Rx) || defined(STM32F412Cx)
573 #define RCC_PLLI2SP_DIV2 0x00000002U
574 #define RCC_PLLI2SP_DIV4 0x00000004U
575 #define RCC_PLLI2SP_DIV6 0x00000006U
576 #define RCC_PLLI2SP_DIV8 0x00000008U
577 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
578 /**
579  * @}
580  */
581 
582 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
583  * @{
584  */
585 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
586 #define RCC_PLLSAIP_DIV2 0x00000002U
587 #define RCC_PLLSAIP_DIV4 0x00000004U
588 #define RCC_PLLSAIP_DIV6 0x00000006U
589 #define RCC_PLLSAIP_DIV8 0x00000008U
590 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
591 /**
592  * @}
593  */
594 
595 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
596 /** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
597  * @{
598  */
599 #define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U
600 #define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U
601 #define RCC_SAIACLKSOURCE_EXT 0x00200000U
602 /**
603  * @}
604  */
605 
606 /** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
607  * @{
608  */
609 #define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U
610 #define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U
611 #define RCC_SAIBCLKSOURCE_EXT 0x00800000U
612 /**
613  * @}
614  */
615 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
616 
617 #if defined(STM32F469xx) || defined(STM32F479xx)
618 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
619  * @{
620  */
621 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
622 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
623 /**
624  * @}
625  */
626 
627 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
628  * @{
629  */
630 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
631 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
632 /**
633  * @}
634  */
635 
636 /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
637  * @{
638  */
639 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
640 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
641 /**
642  * @}
643  */
644 #endif /* STM32F469xx || STM32F479xx */
645 
646 #if defined(STM32F446xx)
647 /** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
648  * @{
649  */
650 #define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U
651 #define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
652 #define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
653 #define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
654 /**
655  * @}
656  */
657 
658 /** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
659  * @{
660  */
661 #define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U
662 #define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
663 #define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
664 #define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
665 /**
666  * @}
667  */
668 
669 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
670  * @{
671  */
672 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
673 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
674 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
675 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
676 /**
677  * @}
678  */
679 
680 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
681  * @{
682  */
683 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
684 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
685 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
686 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
687 /**
688  * @}
689  */
690 
691 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
692  * @{
693  */
694 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
695 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
696 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
697 /**
698  * @}
699  */
700 
701 /** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
702  * @{
703  */
704 #define RCC_CECCLKSOURCE_HSI 0x00000000U
705 #define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
706 /**
707  * @}
708  */
709 
710 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
711  * @{
712  */
713 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
714 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
715 /**
716  * @}
717  */
718 
719 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
720  * @{
721  */
722 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
723 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
724 /**
725  * @}
726  */
727 
728 /** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
729  * @{
730  */
731 #define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U
732 #define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
733 /**
734  * @}
735  */
736 
737 #endif /* STM32F446xx */
738 
739 #if defined(STM32F413xx) || defined(STM32F423xx)
740 /** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source
741  * @{
742  */
743 #define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U
744 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
745 #define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
746 #define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1)
747 /**
748  * @}
749  */
750 
751 /** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source
752  * @{
753  */
754 #define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U
755 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
756 #define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
757 #define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1)
758 /**
759  * @}
760  */
761 
762 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
763  * @{
764  */
765 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
766 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
767 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
768 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
769 /**
770  * @}
771  */
772 
773 
774 /** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source
775  * @{
776  */
777 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U
778 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
779 /**
780  * @}
781  */
782 
783 /** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source
784  * @{
785  */
786 #define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U
787 #define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
788 /**
789  * @}
790  */
791 
792 #endif /* STM32F413xx || STM32F423xx */
793 
794 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
795 /** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
796  * @{
797  */
798 #define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U
799 #define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
800 /**
801  * @}
802  */
803 
804 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source
805  * @{
806  */
807 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U
808 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
809 /**
810  * @}
811  */
812 
813 /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source
814  * @{
815  */
816 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
817 #define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
818 /**
819  * @}
820  */
821 
822 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
823  * @{
824  */
825 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
826 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
827 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
828 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
829 /**
830  * @}
831  */
832 
833 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
834  * @{
835  */
836 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
837 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
838 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
839 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
840 /**
841  * @}
842  */
843 
844 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
845  * @{
846  */
847 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
848 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
849 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
850 /**
851  * @}
852  */
853 
854 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
855  * @{
856  */
857 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
858 #define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
859 /**
860  * @}
861  */
862 
863 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
864  * @{
865  */
866 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
867 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
868 /**
869  * @}
870  */
871 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
872 
873 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
874 
875 /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
876  * @{
877  */
878 #define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U
879 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
880 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
881 /**
882  * @}
883  */
884 
885 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
886  * @{
887  */
888 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
889 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
890 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
891 /**
892  * @}
893  */
894 
895 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
896  * @{
897  */
898 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
899 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
900 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
901 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
902 /**
903  * @}
904  */
905 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
906 
907 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
908  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
909  defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
910  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
911  defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
912 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
913  * @{
914  */
915 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
916 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
917 /**
918  * @}
919  */
920 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
921  STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
922  STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
923 
924 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
925  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
926  defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
927  defined(STM32F423xx)
928 /** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
929  * @{
930  */
931 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
932 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
933 /**
934  * @}
935  */
936 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\
937  STM32F412Rx || STM32F412Cx */
938 
939 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
940  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
941  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
942  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
943  defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
944 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
945  * @{
946  */
947 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U
948 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
949 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
950 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
951 /**
952  * @}
953  */
954 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
955  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
956  STM32F412Rx || STM32F413xx | STM32F423xx */
957 
958 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
959 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
960  * @{
961  */
962 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U
963 #define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
964 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
965 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
966 /**
967  * @}
968  */
969 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
970 
971 /**
972  * @}
973  */
974 
975 /* Exported macro ------------------------------------------------------------*/
976 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
977  * @{
978  */
979 /*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/
980 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
981 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
982  * @brief Enables or disables the AHB1 peripheral clock.
983  * @note After reset, the peripheral clock (used for registers read/write access)
984  * is disabled and the application software has to enable this clock before
985  * using it.
986  * @{
987  */
988 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
989  __IO uint32_t tmpreg = 0x00U; \
990  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
991  /* Delay after an RCC peripheral clock enabling */ \
992  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
993  UNUSED(tmpreg); \
994  } while(0U)
995 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
996  __IO uint32_t tmpreg = 0x00U; \
997  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
998  /* Delay after an RCC peripheral clock enabling */ \
999  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
1000  UNUSED(tmpreg); \
1001  } while(0U)
1002 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
1003  __IO uint32_t tmpreg = 0x00U; \
1004  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
1005  /* Delay after an RCC peripheral clock enabling */ \
1006  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
1007  UNUSED(tmpreg); \
1008  } while(0U)
1009 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
1010  __IO uint32_t tmpreg = 0x00U; \
1011  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
1012  /* Delay after an RCC peripheral clock enabling */ \
1013  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
1014  UNUSED(tmpreg); \
1015  } while(0U)
1016 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
1017  __IO uint32_t tmpreg = 0x00U; \
1018  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
1019  /* Delay after an RCC peripheral clock enabling */ \
1020  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
1021  UNUSED(tmpreg); \
1022  } while(0U)
1023 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
1024  __IO uint32_t tmpreg = 0x00U; \
1025  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
1026  /* Delay after an RCC peripheral clock enabling */ \
1027  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
1028  UNUSED(tmpreg); \
1029  } while(0U)
1030 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
1031  __IO uint32_t tmpreg = 0x00U; \
1032  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
1033  /* Delay after an RCC peripheral clock enabling */ \
1034  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
1035  UNUSED(tmpreg); \
1036  } while(0U)
1037 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1038  __IO uint32_t tmpreg = 0x00U; \
1039  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
1040  /* Delay after an RCC peripheral clock enabling */ \
1041  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
1042  UNUSED(tmpreg); \
1043  } while(0U)
1044 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
1045  __IO uint32_t tmpreg = 0x00U; \
1046  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
1047  /* Delay after an RCC peripheral clock enabling */ \
1048  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
1049  UNUSED(tmpreg); \
1050  } while(0U)
1051 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
1052  __IO uint32_t tmpreg = 0x00U; \
1053  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
1054  /* Delay after an RCC peripheral clock enabling */ \
1055  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
1056  UNUSED(tmpreg); \
1057  } while(0U)
1058 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
1059  __IO uint32_t tmpreg = 0x00U; \
1060  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
1061  /* Delay after an RCC peripheral clock enabling */ \
1062  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
1063  UNUSED(tmpreg); \
1064  } while(0U)
1065 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
1066  __IO uint32_t tmpreg = 0x00U; \
1067  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
1068  /* Delay after an RCC peripheral clock enabling */ \
1069  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
1070  UNUSED(tmpreg); \
1071  } while(0U)
1072 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
1073  __IO uint32_t tmpreg = 0x00U; \
1074  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
1075  /* Delay after an RCC peripheral clock enabling */ \
1076  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
1077  UNUSED(tmpreg); \
1078  } while(0U)
1079 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
1080  __IO uint32_t tmpreg = 0x00U; \
1081  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
1082  /* Delay after an RCC peripheral clock enabling */ \
1083  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
1084  UNUSED(tmpreg); \
1085  } while(0U)
1086 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
1087  __IO uint32_t tmpreg = 0x00U; \
1088  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
1089  /* Delay after an RCC peripheral clock enabling */ \
1090  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
1091  UNUSED(tmpreg); \
1092  } while(0U)
1093 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
1094  __IO uint32_t tmpreg = 0x00U; \
1095  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
1096  /* Delay after an RCC peripheral clock enabling */ \
1097  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
1098  UNUSED(tmpreg); \
1099  } while(0U)
1100 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
1101  __IO uint32_t tmpreg = 0x00U; \
1102  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
1103  /* Delay after an RCC peripheral clock enabling */ \
1104  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
1105  UNUSED(tmpreg); \
1106  } while(0U)
1107 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
1108 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
1109 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
1110 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
1111 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
1112 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
1113 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
1114 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
1115 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
1116 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
1117 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
1118 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
1119 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
1120 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
1121 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
1122 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
1123 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
1124 
1125 /**
1126  * @brief Enable ETHERNET clock.
1127  */
1128 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
1129  __HAL_RCC_ETHMAC_CLK_ENABLE(); \
1130  __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
1131  __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
1132  } while(0U)
1133 /**
1134  * @brief Disable ETHERNET clock.
1135  */
1136 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
1137  __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
1138  __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
1139  __HAL_RCC_ETHMAC_CLK_DISABLE(); \
1140  } while(0U)
1141 /**
1142  * @}
1143  */
1144 
1145 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
1146  * @brief Get the enable or disable status of the AHB1 peripheral clock.
1147  * @note After reset, the peripheral clock (used for registers read/write access)
1148  * is disabled and the application software has to enable this clock before
1149  * using it.
1150  * @{
1151  */
1152 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
1153 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
1154 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
1155 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
1156 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
1157 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
1158 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
1159 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
1160 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
1161 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
1162 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
1163 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
1164 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
1165 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
1166 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
1167 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
1168 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
1169 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
1170  __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
1171  __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
1172 
1173 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
1174 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
1175 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
1176 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
1177 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
1178 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
1179 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
1180 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
1181 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
1182 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
1183 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
1184 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
1185 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
1186 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
1187 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
1188 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
1189 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
1190 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
1191  __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
1192  __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
1193 /**
1194  * @}
1195  */
1196 
1197 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
1198  * @brief Enable or disable the AHB2 peripheral clock.
1199  * @note After reset, the peripheral clock (used for registers read/write access)
1200  * is disabled and the application software has to enable this clock before
1201  * using it.
1202  * @{
1203  */
1204  #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
1205  __IO uint32_t tmpreg = 0x00U; \
1206  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1207  /* Delay after an RCC peripheral clock enabling */ \
1208  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1209  UNUSED(tmpreg); \
1210  } while(0U)
1211 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
1212 
1213 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1214 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
1215  __IO uint32_t tmpreg = 0x00U; \
1216  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1217  /* Delay after an RCC peripheral clock enabling */ \
1218  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1219  UNUSED(tmpreg); \
1220  } while(0U)
1221 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
1222  __IO uint32_t tmpreg = 0x00U; \
1223  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1224  /* Delay after an RCC peripheral clock enabling */ \
1225  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1226  UNUSED(tmpreg); \
1227  } while(0U)
1228 
1229 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
1230 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
1231 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1232 
1233 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
1234  __HAL_RCC_SYSCFG_CLK_ENABLE();\
1235  }while(0U)
1236 
1237 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
1238 
1239 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
1240  __IO uint32_t tmpreg = 0x00U; \
1241  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
1242  /* Delay after an RCC peripheral clock enabling */ \
1243  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
1244  UNUSED(tmpreg); \
1245  } while(0U)
1246 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
1247 /**
1248  * @}
1249  */
1250 
1251 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
1252  * @brief Get the enable or disable status of the AHB1 peripheral clock.
1253  * @note After reset, the peripheral clock (used for registers read/write access)
1254  * is disabled and the application software has to enable this clock before
1255  * using it.
1256  * @{
1257  */
1258 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
1259 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
1260 
1261 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1262 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
1263 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
1264 
1265 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
1266 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
1267 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1268 
1269 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
1270 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
1271 
1272 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
1273 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
1274 /**
1275  * @}
1276  */
1277 
1278 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
1279  * @brief Enables or disables the AHB3 peripheral clock.
1280  * @note After reset, the peripheral clock (used for registers read/write access)
1281  * is disabled and the application software has to enable this clock before
1282  * using it.
1283  * @{
1284  */
1285 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
1286  __IO uint32_t tmpreg = 0x00U; \
1287  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
1288  /* Delay after an RCC peripheral clock enabling */ \
1289  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
1290  UNUSED(tmpreg); \
1291  } while(0U)
1292 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
1293 #if defined(STM32F469xx) || defined(STM32F479xx)
1294 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
1295  __IO uint32_t tmpreg = 0x00U; \
1296  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
1297  /* Delay after an RCC peripheral clock enabling */ \
1298  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
1299  UNUSED(tmpreg); \
1300  } while(0U)
1301 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
1302 #endif /* STM32F469xx || STM32F479xx */
1303 /**
1304  * @}
1305  */
1306 
1307 
1308 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
1309  * @brief Get the enable or disable status of the AHB3 peripheral clock.
1310  * @note After reset, the peripheral clock (used for registers read/write access)
1311  * is disabled and the application software has to enable this clock before
1312  * using it.
1313  * @{
1314  */
1315 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
1316 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
1317 #if defined(STM32F469xx) || defined(STM32F479xx)
1318 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
1319 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
1320 #endif /* STM32F469xx || STM32F479xx */
1321 /**
1322  * @}
1323  */
1324 
1325 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
1326  * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
1327  * @note After reset, the peripheral clock (used for registers read/write access)
1328  * is disabled and the application software has to enable this clock before
1329  * using it.
1330  * @{
1331  */
1332 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
1333  __IO uint32_t tmpreg = 0x00U; \
1334  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
1335  /* Delay after an RCC peripheral clock enabling */ \
1336  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
1337  UNUSED(tmpreg); \
1338  } while(0U)
1339 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
1340  __IO uint32_t tmpreg = 0x00U; \
1341  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
1342  /* Delay after an RCC peripheral clock enabling */ \
1343  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
1344  UNUSED(tmpreg); \
1345  } while(0U)
1346 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
1347  __IO uint32_t tmpreg = 0x00U; \
1348  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1349  /* Delay after an RCC peripheral clock enabling */ \
1350  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1351  UNUSED(tmpreg); \
1352  } while(0U)
1353 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
1354  __IO uint32_t tmpreg = 0x00U; \
1355  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1356  /* Delay after an RCC peripheral clock enabling */ \
1357  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1358  UNUSED(tmpreg); \
1359  } while(0U)
1360 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1361  __IO uint32_t tmpreg = 0x00U; \
1362  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1363  /* Delay after an RCC peripheral clock enabling */ \
1364  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1365  UNUSED(tmpreg); \
1366  } while(0U)
1367 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1368  __IO uint32_t tmpreg = 0x00U; \
1369  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1370  /* Delay after an RCC peripheral clock enabling */ \
1371  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1372  UNUSED(tmpreg); \
1373  } while(0U)
1374 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
1375  __IO uint32_t tmpreg = 0x00U; \
1376  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
1377  /* Delay after an RCC peripheral clock enabling */ \
1378  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
1379  UNUSED(tmpreg); \
1380  } while(0U)
1381 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
1382  __IO uint32_t tmpreg = 0x00U; \
1383  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1384  /* Delay after an RCC peripheral clock enabling */ \
1385  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1386  UNUSED(tmpreg); \
1387  } while(0U)
1388 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
1389  __IO uint32_t tmpreg = 0x00U; \
1390  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1391  /* Delay after an RCC peripheral clock enabling */ \
1392  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1393  UNUSED(tmpreg); \
1394  } while(0U)
1395 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
1396  __IO uint32_t tmpreg = 0x00U; \
1397  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
1398  /* Delay after an RCC peripheral clock enabling */ \
1399  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
1400  UNUSED(tmpreg); \
1401  } while(0U)
1402 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
1403  __IO uint32_t tmpreg = 0x00U; \
1404  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1405  /* Delay after an RCC peripheral clock enabling */ \
1406  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1407  UNUSED(tmpreg); \
1408  } while(0U)
1409 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
1410  __IO uint32_t tmpreg = 0x00U; \
1411  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
1412  /* Delay after an RCC peripheral clock enabling */ \
1413  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
1414  UNUSED(tmpreg); \
1415  } while(0U)
1416 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
1417  __IO uint32_t tmpreg = 0x00U; \
1418  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
1419  /* Delay after an RCC peripheral clock enabling */ \
1420  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
1421  UNUSED(tmpreg); \
1422  } while(0U)
1423 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
1424  __IO uint32_t tmpreg = 0x00U; \
1425  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
1426  /* Delay after an RCC peripheral clock enabling */ \
1427  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
1428  UNUSED(tmpreg); \
1429  } while(0U)
1430 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
1431  __IO uint32_t tmpreg = 0x00U; \
1432  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
1433  /* Delay after an RCC peripheral clock enabling */ \
1434  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
1435  UNUSED(tmpreg); \
1436  } while(0U)
1437 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
1438  __IO uint32_t tmpreg = 0x00U; \
1439  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
1440  /* Delay after an RCC peripheral clock enabling */ \
1441  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
1442  UNUSED(tmpreg); \
1443  } while(0U)
1444 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
1445  __IO uint32_t tmpreg = 0x00U; \
1446  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
1447  /* Delay after an RCC peripheral clock enabling */ \
1448  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
1449  UNUSED(tmpreg); \
1450  } while(0U)
1451 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
1452  __IO uint32_t tmpreg = 0x00U; \
1453  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1454  /* Delay after an RCC peripheral clock enabling */ \
1455  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1456  UNUSED(tmpreg); \
1457  } while(0U)
1458 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
1459  __IO uint32_t tmpreg = 0x00U; \
1460  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1461  /* Delay after an RCC peripheral clock enabling */ \
1462  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1463  UNUSED(tmpreg); \
1464  } while(0U)
1465 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
1466 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
1467 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
1468 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
1469 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
1470 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
1471 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
1472 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
1473 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
1474 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
1475 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
1476 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
1477 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
1478 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
1479 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
1480 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
1481 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
1482 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
1483 /**
1484  * @}
1485  */
1486 
1487 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
1488  * @brief Get the enable or disable status of the APB1 peripheral clock.
1489  * @note After reset, the peripheral clock (used for registers read/write access)
1490  * is disabled and the application software has to enable this clock before
1491  * using it.
1492  * @{
1493  */
1494 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
1495 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
1496 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
1497 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1498 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
1499 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
1500 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
1501 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
1502 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
1503 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
1504 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
1505 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
1506 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
1507 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
1508 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
1509 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
1510 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
1511 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
1512 
1513 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
1514 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
1515 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
1516 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1517 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
1518 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
1519 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
1520 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
1521 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
1522 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
1523 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
1524 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
1525 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
1526 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
1527 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
1528 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
1529 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
1530 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
1531 /**
1532  * @}
1533  */
1534 
1535 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
1536  * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
1537  * @note After reset, the peripheral clock (used for registers read/write access)
1538  * is disabled and the application software has to enable this clock before
1539  * using it.
1540  * @{
1541  */
1542 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
1543  __IO uint32_t tmpreg = 0x00U; \
1544  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1545  /* Delay after an RCC peripheral clock enabling */ \
1546  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1547  UNUSED(tmpreg); \
1548  } while(0U)
1549 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
1550  __IO uint32_t tmpreg = 0x00U; \
1551  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1552  /* Delay after an RCC peripheral clock enabling */ \
1553  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1554  UNUSED(tmpreg); \
1555  } while(0U)
1556 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
1557  __IO uint32_t tmpreg = 0x00U; \
1558  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1559  /* Delay after an RCC peripheral clock enabling */ \
1560  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1561  UNUSED(tmpreg); \
1562  } while(0U)
1563 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
1564  __IO uint32_t tmpreg = 0x00U; \
1565  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1566  /* Delay after an RCC peripheral clock enabling */ \
1567  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1568  UNUSED(tmpreg); \
1569  } while(0U)
1570 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
1571  __IO uint32_t tmpreg = 0x00U; \
1572  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
1573  /* Delay after an RCC peripheral clock enabling */ \
1574  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
1575  UNUSED(tmpreg); \
1576  } while(0U)
1577 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
1578  __IO uint32_t tmpreg = 0x00U; \
1579  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
1580  /* Delay after an RCC peripheral clock enabling */ \
1581  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
1582  UNUSED(tmpreg); \
1583  } while(0U)
1584 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
1585  __IO uint32_t tmpreg = 0x00U; \
1586  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
1587  /* Delay after an RCC peripheral clock enabling */ \
1588  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
1589  UNUSED(tmpreg); \
1590  } while(0U)
1591 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
1592  __IO uint32_t tmpreg = 0x00U; \
1593  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
1594  /* Delay after an RCC peripheral clock enabling */ \
1595  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
1596  UNUSED(tmpreg); \
1597  } while(0U)
1598 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
1599  __IO uint32_t tmpreg = 0x00U; \
1600  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1601  /* Delay after an RCC peripheral clock enabling */ \
1602  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1603  UNUSED(tmpreg); \
1604  } while(0U)
1605 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
1606 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
1607 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1608 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
1609 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
1610 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
1611 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
1612 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
1613 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
1614 
1615 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
1616 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
1617  __IO uint32_t tmpreg = 0x00U; \
1618  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
1619  /* Delay after an RCC peripheral clock enabling */ \
1620  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
1621  UNUSED(tmpreg); \
1622  } while(0U)
1623 
1624 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
1625 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
1626 
1627 #if defined(STM32F469xx) || defined(STM32F479xx)
1628 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
1629  __IO uint32_t tmpreg = 0x00U; \
1630  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
1631  /* Delay after an RCC peripheral clock enabling */ \
1632  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
1633  UNUSED(tmpreg); \
1634  } while(0U)
1635 
1636 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
1637 #endif /* STM32F469xx || STM32F479xx */
1638 /**
1639  * @}
1640  */
1641 
1642 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
1643  * @brief Get the enable or disable status of the APB2 peripheral clock.
1644  * @note After reset, the peripheral clock (used for registers read/write access)
1645  * is disabled and the application software has to enable this clock before
1646  * using it.
1647  * @{
1648  */
1649 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
1650 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
1651 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
1652 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
1653 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
1654 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
1655 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
1656 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
1657 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
1658 
1659 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
1660 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
1661 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
1662 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
1663 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
1664 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
1665 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
1666 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
1667 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
1668 
1669 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
1670 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
1671 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
1672 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
1673 
1674 #if defined(STM32F469xx) || defined(STM32F479xx)
1675 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
1676 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
1677 #endif /* STM32F469xx || STM32F479xx */
1678 /**
1679  * @}
1680  */
1681 
1682 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
1683  * @brief Force or release AHB1 peripheral reset.
1684  * @{
1685  */
1686 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
1687 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
1688 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
1689 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
1690 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
1691 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
1692 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
1693 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
1694 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
1695 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
1696 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
1697 
1698 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
1699 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
1700 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
1701 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
1702 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
1703 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
1704 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
1705 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
1706 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
1707 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
1708 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
1709 /**
1710  * @}
1711  */
1712 
1713 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
1714  * @brief Force or release AHB2 peripheral reset.
1715  * @{
1716  */
1717 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
1718 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
1719 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
1720 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
1721 
1722 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
1723 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
1724 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
1725 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
1726 
1727 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1728 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
1729 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
1730 
1731 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
1732 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
1733 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1734 /**
1735  * @}
1736  */
1737 
1738 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
1739  * @brief Force or release AHB3 peripheral reset.
1740  * @{
1741  */
1742 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
1743 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
1744 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
1745 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
1746 
1747 #if defined(STM32F469xx) || defined(STM32F479xx)
1748 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
1749 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
1750 #endif /* STM32F469xx || STM32F479xx */
1751 /**
1752  * @}
1753  */
1754 
1755 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
1756  * @brief Force or release APB1 peripheral reset.
1757  * @{
1758  */
1759 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1760 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1761 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1762 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1763 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1764 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1765 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1766 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1767 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
1768 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
1769 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1770 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
1771 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
1772 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
1773 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
1774 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
1775 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1776 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
1777 
1778 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
1779 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
1780 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
1781 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1782 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
1783 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1784 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1785 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1786 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1787 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1788 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1789 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1790 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1791 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
1792 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
1793 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1794 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
1795 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
1796 /**
1797  * @}
1798  */
1799 
1800 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
1801  * @brief Force or release APB2 peripheral reset.
1802  * @{
1803  */
1804 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
1805 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
1806 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
1807 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
1808 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
1809 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
1810 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
1811 
1812 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
1813 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
1814 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
1815 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
1816 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
1817 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
1818 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
1819 
1820 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
1821 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
1822 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
1823 #endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
1824 
1825 #if defined(STM32F469xx) || defined(STM32F479xx)
1826 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
1827 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
1828 #endif /* STM32F469xx || STM32F479xx */
1829 /**
1830  * @}
1831  */
1832 
1833 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
1834  * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
1835  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1836  * power consumption.
1837  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1838  * @note By default, all peripheral clocks are enabled during SLEEP mode.
1839  * @{
1840  */
1841 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
1842 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
1843 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
1844 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
1845 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
1846 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
1847 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
1848 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
1849 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
1850 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
1851 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
1852 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
1853 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
1854 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
1855 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
1856 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
1857 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
1858 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
1859 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
1860 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
1861 
1862 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
1863 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
1864 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
1865 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
1866 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
1867 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
1868 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
1869 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
1870 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
1871 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
1872 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
1873 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
1874 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
1875 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
1876 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
1877 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
1878 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
1879 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
1880 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
1881 /**
1882  * @}
1883  */
1884 
1885 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
1886  * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
1887  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1888  * power consumption.
1889  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
1890  * @note By default, all peripheral clocks are enabled during SLEEP mode.
1891  * @{
1892  */
1893 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
1894 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
1895 
1896 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
1897 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
1898 
1899 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
1900 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
1901 
1902 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1903 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
1904 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
1905 
1906 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
1907 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
1908 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1909 /**
1910  * @}
1911  */
1912 
1913 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
1914  * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
1915  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1916  * power consumption.
1917  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1918  * @note By default, all peripheral clocks are enabled during SLEEP mode.
1919  * @{
1920  */
1921 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
1922 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
1923 
1924 #if defined(STM32F469xx) || defined(STM32F479xx)
1925 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
1926 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
1927 #endif /* STM32F469xx || STM32F479xx */
1928 /**
1929  * @}
1930  */
1931 
1932 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
1933  * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
1934  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1935  * power consumption.
1936  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1937  * @note By default, all peripheral clocks are enabled during SLEEP mode.
1938  * @{
1939  */
1940 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
1941 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
1942 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
1943 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
1944 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
1945 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
1946 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
1947 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
1948 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
1949 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
1950 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
1951 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
1952 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
1953 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
1954 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
1955 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
1956 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
1957 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
1958 
1959 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
1960 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
1961 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
1962 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
1963 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
1964 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
1965 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
1966 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
1967 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
1968 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
1969 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
1970 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
1971 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
1972 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
1973 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
1974 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
1975 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
1976 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
1977 /**
1978  * @}
1979  */
1980 
1981 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
1982  * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
1983  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1984  * power consumption.
1985  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1986  * @note By default, all peripheral clocks are enabled during SLEEP mode.
1987  * @{
1988  */
1989 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
1990 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
1991 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
1992 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
1993 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
1994 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
1995 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
1996 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
1997 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
1998 
1999 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
2000 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
2001 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
2002 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
2003 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
2004 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
2005 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
2006 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
2007 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
2008 
2009 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
2010 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
2011 
2012 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
2013 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
2014 
2015 #if defined(STM32F469xx) || defined(STM32F479xx)
2016 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
2017 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
2018 #endif /* STM32F469xx || STM32F479xx */
2019 /**
2020  * @}
2021  */
2022 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
2023 /*----------------------------------------------------------------------------*/
2024 
2025 /*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/
2026 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
2027 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
2028  * @brief Enables or disables the AHB1 peripheral clock.
2029  * @note After reset, the peripheral clock (used for registers read/write access)
2030  * is disabled and the application software has to enable this clock before
2031  * using it.
2032  * @{
2033  */
2034 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
2035  __IO uint32_t tmpreg = 0x00U; \
2036  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
2037  /* Delay after an RCC peripheral clock enabling */ \
2038  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
2039  UNUSED(tmpreg); \
2040  } while(0U)
2041 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
2042  __IO uint32_t tmpreg = 0x00U; \
2043  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
2044  /* Delay after an RCC peripheral clock enabling */ \
2045  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
2046  UNUSED(tmpreg); \
2047  } while(0U)
2048 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
2049  __IO uint32_t tmpreg = 0x00U; \
2050  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
2051  /* Delay after an RCC peripheral clock enabling */ \
2052  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
2053  UNUSED(tmpreg); \
2054  } while(0U)
2055 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
2056  __IO uint32_t tmpreg = 0x00U; \
2057  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2058  /* Delay after an RCC peripheral clock enabling */ \
2059  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2060  UNUSED(tmpreg); \
2061  } while(0U)
2062 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
2063  __IO uint32_t tmpreg = 0x00U; \
2064  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
2065  /* Delay after an RCC peripheral clock enabling */ \
2066  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
2067  UNUSED(tmpreg); \
2068  } while(0U)
2069 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
2070  __IO uint32_t tmpreg = 0x00U; \
2071  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
2072  /* Delay after an RCC peripheral clock enabling */ \
2073  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
2074  UNUSED(tmpreg); \
2075  } while(0U)
2076 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
2077  __IO uint32_t tmpreg = 0x00U; \
2078  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
2079  /* Delay after an RCC peripheral clock enabling */ \
2080  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
2081  UNUSED(tmpreg); \
2082  } while(0U)
2083 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
2084  __IO uint32_t tmpreg = 0x00U; \
2085  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
2086  /* Delay after an RCC peripheral clock enabling */ \
2087  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
2088  UNUSED(tmpreg); \
2089  } while(0U)
2090 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
2091  __IO uint32_t tmpreg = 0x00U; \
2092  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
2093  /* Delay after an RCC peripheral clock enabling */ \
2094  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
2095  UNUSED(tmpreg); \
2096  } while(0U)
2097 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
2098  __IO uint32_t tmpreg = 0x00U; \
2099  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
2100  /* Delay after an RCC peripheral clock enabling */ \
2101  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
2102  UNUSED(tmpreg); \
2103  } while(0U)
2104 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
2105 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
2106 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
2107 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
2108 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
2109 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
2110 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
2111 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
2112 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
2113 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
2114 #if defined(STM32F407xx)|| defined(STM32F417xx)
2115 /**
2116  * @brief Enable ETHERNET clock.
2117  */
2118 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
2119  __IO uint32_t tmpreg = 0x00U; \
2120  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
2121  /* Delay after an RCC peripheral clock enabling */ \
2122  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
2123  UNUSED(tmpreg); \
2124  } while(0U)
2125 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
2126  __IO uint32_t tmpreg = 0x00U; \
2127  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
2128  /* Delay after an RCC peripheral clock enabling */ \
2129  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
2130  UNUSED(tmpreg); \
2131  } while(0U)
2132 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
2133  __IO uint32_t tmpreg = 0x00U; \
2134  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
2135  /* Delay after an RCC peripheral clock enabling */ \
2136  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
2137  UNUSED(tmpreg); \
2138  } while(0U)
2139 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
2140  __IO uint32_t tmpreg = 0x00U; \
2141  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
2142  /* Delay after an RCC peripheral clock enabling */ \
2143  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
2144  UNUSED(tmpreg); \
2145  } while(0U)
2146 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
2147  __HAL_RCC_ETHMAC_CLK_ENABLE(); \
2148  __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
2149  __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
2150  } while(0U)
2151 
2152 /**
2153  * @brief Disable ETHERNET clock.
2154  */
2155 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
2156 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
2157 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
2158 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
2159 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
2160  __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
2161  __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
2162  __HAL_RCC_ETHMAC_CLK_DISABLE(); \
2163  } while(0U)
2164 #endif /* STM32F407xx || STM32F417xx */
2165 /**
2166  * @}
2167  */
2168 
2169 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
2170  * @brief Get the enable or disable status of the AHB1 peripheral clock.
2171  * @note After reset, the peripheral clock (used for registers read/write access)
2172  * is disabled and the application software has to enable this clock before
2173  * using it.
2174  * @{
2175  */
2176 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
2177 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
2178 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
2179 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
2180 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
2181 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
2182 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
2183 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
2184 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
2185 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
2186 
2187 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
2188 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
2189 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
2190 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
2191 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
2192 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
2193 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
2194 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
2195 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
2196 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
2197 #if defined(STM32F407xx)|| defined(STM32F417xx)
2198 /**
2199  * @brief Enable ETHERNET clock.
2200  */
2201 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
2202 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
2203 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
2204 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
2205 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
2206  __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
2207  __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
2208 /**
2209  * @brief Disable ETHERNET clock.
2210  */
2211 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
2212 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
2213 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
2214 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
2215 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
2216  __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
2217  __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
2218 #endif /* STM32F407xx || STM32F417xx */
2219 /**
2220  * @}
2221  */
2222 
2223 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
2224  * @brief Enable or disable the AHB2 peripheral clock.
2225  * @note After reset, the peripheral clock (used for registers read/write access)
2226  * is disabled and the application software has to enable this clock before
2227  * using it.
2228  * @{
2229  */
2230 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
2231  __HAL_RCC_SYSCFG_CLK_ENABLE();\
2232  }while(0U)
2233 
2234 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
2235 
2236 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
2237  __IO uint32_t tmpreg = 0x00U; \
2238  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
2239  /* Delay after an RCC peripheral clock enabling */ \
2240  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
2241  UNUSED(tmpreg); \
2242  } while(0U)
2243 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
2244 
2245 #if defined(STM32F407xx)|| defined(STM32F417xx)
2246 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
2247  __IO uint32_t tmpreg = 0x00U; \
2248  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
2249  /* Delay after an RCC peripheral clock enabling */ \
2250  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
2251  UNUSED(tmpreg); \
2252  } while(0U)
2253 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
2254 #endif /* STM32F407xx || STM32F417xx */
2255 
2256 #if defined(STM32F415xx) || defined(STM32F417xx)
2257 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
2258  __IO uint32_t tmpreg = 0x00U; \
2259  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
2260  /* Delay after an RCC peripheral clock enabling */ \
2261  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
2262  UNUSED(tmpreg); \
2263  } while(0U)
2264 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
2265  __IO uint32_t tmpreg = 0x00U; \
2266  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
2267  /* Delay after an RCC peripheral clock enabling */ \
2268  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
2269  UNUSED(tmpreg); \
2270  } while(0U)
2271 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
2272 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
2273 #endif /* STM32F415xx || STM32F417xx */
2274 /**
2275  * @}
2276  */
2277 
2278 
2279 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
2280  * @brief Get the enable or disable status of the AHB2 peripheral clock.
2281  * @note After reset, the peripheral clock (used for registers read/write access)
2282  * is disabled and the application software has to enable this clock before
2283  * using it.
2284  * @{
2285  */
2286 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
2287 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
2288 
2289 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
2290 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
2291 
2292 #if defined(STM32F407xx)|| defined(STM32F417xx)
2293 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
2294 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
2295 #endif /* STM32F407xx || STM32F417xx */
2296 
2297 #if defined(STM32F415xx) || defined(STM32F417xx)
2298 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
2299 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
2300 
2301 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
2302 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
2303 #endif /* STM32F415xx || STM32F417xx */
2304 /**
2305  * @}
2306  */
2307 
2308 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
2309  * @brief Enables or disables the AHB3 peripheral clock.
2310  * @note After reset, the peripheral clock (used for registers read/write access)
2311  * is disabled and the application software has to enable this clock before
2312  * using it.
2313  * @{
2314  */
2315 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
2316  __IO uint32_t tmpreg = 0x00U; \
2317  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
2318  /* Delay after an RCC peripheral clock enabling */ \
2319  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
2320  UNUSED(tmpreg); \
2321  } while(0U)
2322 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
2323 /**
2324  * @}
2325  */
2326 
2327 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
2328  * @brief Get the enable or disable status of the AHB3 peripheral clock.
2329  * @note After reset, the peripheral clock (used for registers read/write access)
2330  * is disabled and the application software has to enable this clock before
2331  * using it.
2332  * @{
2333  */
2334 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
2335 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
2336 /**
2337  * @}
2338  */
2339 
2340 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
2341  * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
2342  * @note After reset, the peripheral clock (used for registers read/write access)
2343  * is disabled and the application software has to enable this clock before
2344  * using it.
2345  * @{
2346  */
2347 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
2348  __IO uint32_t tmpreg = 0x00U; \
2349  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
2350  /* Delay after an RCC peripheral clock enabling */ \
2351  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
2352  UNUSED(tmpreg); \
2353  } while(0U)
2354 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
2355  __IO uint32_t tmpreg = 0x00U; \
2356  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
2357  /* Delay after an RCC peripheral clock enabling */ \
2358  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
2359  UNUSED(tmpreg); \
2360  } while(0U)
2361 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
2362  __IO uint32_t tmpreg = 0x00U; \
2363  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
2364  /* Delay after an RCC peripheral clock enabling */ \
2365  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
2366  UNUSED(tmpreg); \
2367  } while(0U)
2368 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
2369  __IO uint32_t tmpreg = 0x00U; \
2370  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
2371  /* Delay after an RCC peripheral clock enabling */ \
2372  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
2373  UNUSED(tmpreg); \
2374  } while(0U)
2375 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
2376  __IO uint32_t tmpreg = 0x00U; \
2377  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
2378  /* Delay after an RCC peripheral clock enabling */ \
2379  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
2380  UNUSED(tmpreg); \
2381  } while(0U)
2382 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
2383  __IO uint32_t tmpreg = 0x00U; \
2384  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
2385  /* Delay after an RCC peripheral clock enabling */ \
2386  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
2387  UNUSED(tmpreg); \
2388  } while(0U)
2389 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
2390  __IO uint32_t tmpreg = 0x00U; \
2391  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
2392  /* Delay after an RCC peripheral clock enabling */ \
2393  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
2394  UNUSED(tmpreg); \
2395  } while(0U)
2396 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
2397  __IO uint32_t tmpreg = 0x00U; \
2398  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
2399  /* Delay after an RCC peripheral clock enabling */ \
2400  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
2401  UNUSED(tmpreg); \
2402  } while(0U)
2403 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
2404  __IO uint32_t tmpreg = 0x00U; \
2405  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
2406  /* Delay after an RCC peripheral clock enabling */ \
2407  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
2408  UNUSED(tmpreg); \
2409  } while(0U)
2410 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
2411  __IO uint32_t tmpreg = 0x00U; \
2412  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
2413  /* Delay after an RCC peripheral clock enabling */ \
2414  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
2415  UNUSED(tmpreg); \
2416  } while(0U)
2417 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
2418  __IO uint32_t tmpreg = 0x00U; \
2419  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
2420  /* Delay after an RCC peripheral clock enabling */ \
2421  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
2422  UNUSED(tmpreg); \
2423  } while(0U)
2424 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
2425  __IO uint32_t tmpreg = 0x00U; \
2426  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
2427  /* Delay after an RCC peripheral clock enabling */ \
2428  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
2429  UNUSED(tmpreg); \
2430  } while(0U)
2431 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
2432  __IO uint32_t tmpreg = 0x00U; \
2433  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2434  /* Delay after an RCC peripheral clock enabling */ \
2435  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2436  UNUSED(tmpreg); \
2437  } while(0U)
2438 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
2439  __IO uint32_t tmpreg = 0x00U; \
2440  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2441  /* Delay after an RCC peripheral clock enabling */ \
2442  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2443  UNUSED(tmpreg); \
2444  } while(0U)
2445 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
2446  __IO uint32_t tmpreg = 0x00U; \
2447  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2448  /* Delay after an RCC peripheral clock enabling */ \
2449  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2450  UNUSED(tmpreg); \
2451  } while(0U)
2452 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
2453  __IO uint32_t tmpreg = 0x00U; \
2454  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2455  /* Delay after an RCC peripheral clock enabling */ \
2456  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2457  UNUSED(tmpreg); \
2458  } while(0U)
2459 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
2460 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
2461 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
2462 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2463 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
2464 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
2465 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
2466 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
2467 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
2468 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
2469 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
2470 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
2471 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
2472 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
2473 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
2474 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
2475 /**
2476  * @}
2477  */
2478 
2479 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
2480  * @brief Get the enable or disable status of the APB1 peripheral clock.
2481  * @note After reset, the peripheral clock (used for registers read/write access)
2482  * is disabled and the application software has to enable this clock before
2483  * using it.
2484  * @{
2485  */
2486 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
2487 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
2488 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
2489 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
2490 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
2491 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
2492 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
2493 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
2494 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
2495 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
2496 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
2497 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
2498 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
2499 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
2500 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
2501 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
2502 
2503 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
2504 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
2505 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
2506 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
2507 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
2508 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
2509 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
2510 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
2511 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
2512 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
2513 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
2514 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
2515 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
2516 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
2517 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
2518 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
2519  /**
2520  * @}
2521  */
2522 
2523 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
2524  * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
2525  * @note After reset, the peripheral clock (used for registers read/write access)
2526  * is disabled and the application software has to enable this clock before
2527  * using it.
2528  * @{
2529  */
2530 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
2531  __IO uint32_t tmpreg = 0x00U; \
2532  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2533  /* Delay after an RCC peripheral clock enabling */ \
2534  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2535  UNUSED(tmpreg); \
2536  } while(0U)
2537 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
2538  __IO uint32_t tmpreg = 0x00U; \
2539  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
2540  /* Delay after an RCC peripheral clock enabling */ \
2541  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
2542  UNUSED(tmpreg); \
2543  } while(0U)
2544 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
2545  __IO uint32_t tmpreg = 0x00U; \
2546  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
2547  /* Delay after an RCC peripheral clock enabling */ \
2548  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
2549  UNUSED(tmpreg); \
2550  } while(0U)
2551 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
2552  __IO uint32_t tmpreg = 0x00U; \
2553  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
2554  /* Delay after an RCC peripheral clock enabling */ \
2555  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
2556  UNUSED(tmpreg); \
2557  } while(0U)
2558 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
2559  __IO uint32_t tmpreg = 0x00U; \
2560  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2561  /* Delay after an RCC peripheral clock enabling */ \
2562  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2563  UNUSED(tmpreg); \
2564  } while(0U)
2565 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
2566  __IO uint32_t tmpreg = 0x00U; \
2567  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
2568  /* Delay after an RCC peripheral clock enabling */ \
2569  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
2570  UNUSED(tmpreg); \
2571  } while(0U)
2572 
2573 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
2574 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
2575 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
2576 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
2577 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
2578 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
2579 /**
2580  * @}
2581  */
2582 
2583 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
2584  * @brief Get the enable or disable status of the APB2 peripheral clock.
2585  * @note After reset, the peripheral clock (used for registers read/write access)
2586  * is disabled and the application software has to enable this clock before
2587  * using it.
2588  * @{
2589  */
2590 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
2591 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
2592 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
2593 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
2594 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
2595 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
2596 
2597 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
2598 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
2599 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
2600 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
2601 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
2602 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
2603 /**
2604  * @}
2605  */
2606 
2607 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
2608  * @brief Force or release AHB1 peripheral reset.
2609  * @{
2610  */
2611 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
2612 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
2613 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
2614 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
2615 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
2616 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
2617 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
2618 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
2619 
2620 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
2621 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
2622 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
2623 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
2624 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
2625 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
2626 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
2627 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
2628 /**
2629  * @}
2630  */
2631 
2632 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
2633  * @brief Force or release AHB2 peripheral reset.
2634  * @{
2635  */
2636 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
2637 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
2638 
2639 #if defined(STM32F407xx)|| defined(STM32F417xx)
2640 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
2641 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
2642 #endif /* STM32F407xx || STM32F417xx */
2643 
2644 #if defined(STM32F415xx) || defined(STM32F417xx)
2645 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
2646 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
2647 
2648 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
2649 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
2650 #endif /* STM32F415xx || STM32F417xx */
2651 
2652 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
2653 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
2654 
2655 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
2656 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
2657 /**
2658  * @}
2659  */
2660 
2661 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
2662  * @brief Force or release AHB3 peripheral reset.
2663  * @{
2664  */
2665 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
2666 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
2667 
2668 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
2669 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
2670 /**
2671  * @}
2672  */
2673 
2674 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
2675  * @brief Force or release APB1 peripheral reset.
2676  * @{
2677  */
2678 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
2679 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
2680 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
2681 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
2682 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
2683 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
2684 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
2685 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
2686 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
2687 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
2688 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
2689 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
2690 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
2691 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
2692 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
2693 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
2694 
2695 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
2696 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
2697 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
2698 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
2699 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
2700 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
2701 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
2702 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
2703 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
2704 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
2705 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
2706 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
2707 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
2708 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
2709 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
2710 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
2711 /**
2712  * @}
2713  */
2714 
2715 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
2716  * @brief Force or release APB2 peripheral reset.
2717  * @{
2718  */
2719 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
2720 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
2721 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
2722 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
2723 
2724 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
2725 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
2726 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
2727 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
2728 /**
2729  * @}
2730  */
2731 
2732 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
2733  * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
2734  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2735  * power consumption.
2736  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2737  * @note By default, all peripheral clocks are enabled during SLEEP mode.
2738  * @{
2739  */
2740 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
2741 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
2742 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
2743 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
2744 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
2745 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
2746 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
2747 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
2748 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
2749 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
2750 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
2751 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
2752 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
2753 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
2754 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
2755 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
2756 
2757 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
2758 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
2759 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
2760 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
2761 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
2762 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
2763 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
2764 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
2765 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
2766 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
2767 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
2768 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
2769 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
2770 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
2771 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
2772 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
2773 /**
2774  * @}
2775  */
2776 
2777 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
2778  * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
2779  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2780  * power consumption.
2781  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
2782  * @note By default, all peripheral clocks are enabled during SLEEP mode.
2783  * @{
2784  */
2785 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
2786 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
2787 
2788 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
2789 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
2790 
2791 #if defined(STM32F407xx)|| defined(STM32F417xx)
2792 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
2793 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
2794 #endif /* STM32F407xx || STM32F417xx */
2795 
2796 #if defined(STM32F415xx) || defined(STM32F417xx)
2797 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
2798 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
2799 
2800 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
2801 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
2802 #endif /* STM32F415xx || STM32F417xx */
2803 /**
2804  * @}
2805  */
2806 
2807 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
2808  * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
2809  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2810  * power consumption.
2811  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2812  * @note By default, all peripheral clocks are enabled during SLEEP mode.
2813  * @{
2814  */
2815 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
2816 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
2817 /**
2818  * @}
2819  */
2820 
2821 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
2822  * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
2823  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2824  * power consumption.
2825  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2826  * @note By default, all peripheral clocks are enabled during SLEEP mode.
2827  * @{
2828  */
2829 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
2830 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
2831 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
2832 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
2833 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
2834 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
2835 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
2836 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
2837 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
2838 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
2839 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
2840 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
2841 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
2842 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
2843 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
2844 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
2845 
2846 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
2847 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
2848 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
2849 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
2850 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
2851 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
2852 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
2853 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
2854 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
2855 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
2856 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
2857 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
2858 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
2859 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
2860 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
2861 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
2862 /**
2863  * @}
2864  */
2865 
2866 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
2867  * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
2868  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2869  * power consumption.
2870  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2871  * @note By default, all peripheral clocks are enabled during SLEEP mode.
2872  * @{
2873  */
2874 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
2875 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
2876 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
2877 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
2878 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
2879 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
2880 
2881 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
2882 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
2883 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
2884 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
2885 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
2886 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
2887 /**
2888  * @}
2889  */
2890 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
2891 /*----------------------------------------------------------------------------*/
2892 
2893 /*------------------------- STM32F401xE/STM32F401xC --------------------------*/
2894 #if defined(STM32F401xC) || defined(STM32F401xE)
2895 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
2896  * @brief Enable or disable the AHB1 peripheral clock.
2897  * @note After reset, the peripheral clock (used for registers read/write access)
2898  * is disabled and the application software has to enable this clock before
2899  * using it.
2900  * @{
2901  */
2902 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
2903  __IO uint32_t tmpreg = 0x00U; \
2904  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2905  /* Delay after an RCC peripheral clock enabling */ \
2906  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2907  UNUSED(tmpreg); \
2908  } while(0U)
2909 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
2910  __IO uint32_t tmpreg = 0x00U; \
2911  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
2912  /* Delay after an RCC peripheral clock enabling */ \
2913  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
2914  UNUSED(tmpreg); \
2915  } while(0U)
2916 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
2917  __IO uint32_t tmpreg = 0x00U; \
2918  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
2919  /* Delay after an RCC peripheral clock enabling */ \
2920  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
2921  UNUSED(tmpreg); \
2922  } while(0U)
2923 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
2924  __IO uint32_t tmpreg = 0x00U; \
2925  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
2926  /* Delay after an RCC peripheral clock enabling */ \
2927  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
2928  UNUSED(tmpreg); \
2929  } while(0U)
2930 
2931 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
2932 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
2933 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
2934 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
2935 /**
2936  * @}
2937  */
2938 
2939 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
2940  * @brief Get the enable or disable status of the AHB1 peripheral clock.
2941  * @note After reset, the peripheral clock (used for registers read/write access)
2942  * is disabled and the application software has to enable this clock before
2943  * using it.
2944  * @{
2945  */
2946 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
2947 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
2948 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
2949 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
2950 
2951 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
2952 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
2953 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
2954 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
2955 /**
2956  * @}
2957  */
2958 
2959 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
2960  * @brief Enable or disable the AHB2 peripheral clock.
2961  * @note After reset, the peripheral clock (used for registers read/write access)
2962  * is disabled and the application software has to enable this clock before
2963  * using it.
2964  * @{
2965  */
2966 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
2967  __HAL_RCC_SYSCFG_CLK_ENABLE();\
2968  }while(0U)
2969 
2970 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
2971 /**
2972  * @}
2973  */
2974 
2975 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
2976  * @brief Get the enable or disable status of the AHB2 peripheral clock.
2977  * @note After reset, the peripheral clock (used for registers read/write access)
2978  * is disabled and the application software has to enable this clock before
2979  * using it.
2980  * @{
2981  */
2982 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
2983 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
2984 /**
2985  * @}
2986  */
2987 
2988 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
2989  * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
2990  * @note After reset, the peripheral clock (used for registers read/write access)
2991  * is disabled and the application software has to enable this clock before
2992  * using it.
2993  * @{
2994  */
2995 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
2996  __IO uint32_t tmpreg = 0x00U; \
2997  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
2998  /* Delay after an RCC peripheral clock enabling */ \
2999  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
3000  UNUSED(tmpreg); \
3001  } while(0U)
3002 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
3003  __IO uint32_t tmpreg = 0x00U; \
3004  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
3005  /* Delay after an RCC peripheral clock enabling */ \
3006  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
3007  UNUSED(tmpreg); \
3008  } while(0U)
3009 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
3010  __IO uint32_t tmpreg = 0x00U; \
3011  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
3012  /* Delay after an RCC peripheral clock enabling */ \
3013  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
3014  UNUSED(tmpreg); \
3015  } while(0U)
3016 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
3017  __IO uint32_t tmpreg = 0x00U; \
3018  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
3019  /* Delay after an RCC peripheral clock enabling */ \
3020  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
3021  UNUSED(tmpreg); \
3022  } while(0U)
3023 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
3024  __IO uint32_t tmpreg = 0x00U; \
3025  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
3026  /* Delay after an RCC peripheral clock enabling */ \
3027  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
3028  UNUSED(tmpreg); \
3029  } while(0U)
3030 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
3031 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
3032 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
3033 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
3034 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
3035 /**
3036  * @}
3037  */
3038 
3039 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
3040  * @brief Get the enable or disable status of the APB1 peripheral clock.
3041  * @note After reset, the peripheral clock (used for registers read/write access)
3042  * is disabled and the application software has to enable this clock before
3043  * using it.
3044  * @{
3045  */
3046 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
3047 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
3048 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
3049 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
3050 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
3051 
3052 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
3053 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
3054 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
3055 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
3056 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
3057 /**
3058  * @}
3059  */
3060 
3061 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
3062  * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
3063  * @note After reset, the peripheral clock (used for registers read/write access)
3064  * is disabled and the application software has to enable this clock before
3065  * using it.
3066  * @{
3067  */
3068 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
3069  __IO uint32_t tmpreg = 0x00U; \
3070  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
3071  /* Delay after an RCC peripheral clock enabling */ \
3072  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
3073  UNUSED(tmpreg); \
3074  } while(0U)
3075 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
3076  __IO uint32_t tmpreg = 0x00U; \
3077  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3078  /* Delay after an RCC peripheral clock enabling */ \
3079  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3080  UNUSED(tmpreg); \
3081  } while(0U)
3082 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
3083  __IO uint32_t tmpreg = 0x00U; \
3084  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3085  /* Delay after an RCC peripheral clock enabling */ \
3086  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3087  UNUSED(tmpreg); \
3088  } while(0U)
3089 
3090 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
3091 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
3092 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
3093 /**
3094  * @}
3095  */
3096 
3097 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
3098  * @brief Get the enable or disable status of the APB2 peripheral clock.
3099  * @note After reset, the peripheral clock (used for registers read/write access)
3100  * is disabled and the application software has to enable this clock before
3101  * using it.
3102  * @{
3103  */
3104 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
3105 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
3106 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
3107 
3108 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
3109 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
3110 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
3111 /**
3112  * @}
3113  */
3114 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
3115  * @brief Force or release AHB1 peripheral reset.
3116  * @{
3117  */
3118 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
3119 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
3120 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
3121 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
3122 
3123 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
3124 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
3125 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
3126 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
3127 /**
3128  * @}
3129  */
3130 
3131 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
3132  * @brief Force or release AHB2 peripheral reset.
3133  * @{
3134  */
3135 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
3136 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
3137 
3138 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
3139 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
3140 /**
3141  * @}
3142  */
3143 
3144 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
3145  * @brief Force or release APB1 peripheral reset.
3146  * @{
3147  */
3148 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
3149 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
3150 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
3151 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
3152 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
3153 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
3154 
3155 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
3156 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
3157 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
3158 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
3159 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
3160 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
3161 /**
3162  * @}
3163  */
3164 
3165 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
3166  * @brief Force or release APB2 peripheral reset.
3167  * @{
3168  */
3169 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
3170 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
3171 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
3172 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
3173 
3174 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
3175 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
3176 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
3177 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
3178 /**
3179  * @}
3180  */
3181 
3182 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
3183  * @brief Force or release AHB3 peripheral reset.
3184  * @{
3185  */
3186 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
3187 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
3188 /**
3189  * @}
3190  */
3191 
3192 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
3193  * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
3194  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
3195  * power consumption.
3196  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
3197  * @note By default, all peripheral clocks are enabled during SLEEP mode.
3198  * @{
3199  */
3200 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
3201 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
3202 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
3203 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
3204 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
3205 
3206 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
3207 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
3208 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
3209 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
3210 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
3211 /**
3212  * @}
3213  */
3214 
3215 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
3216  * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
3217  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
3218  * power consumption.
3219  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
3220  * @note By default, all peripheral clocks are enabled during SLEEP mode.
3221  * @{
3222  */
3223 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
3224 
3225 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
3226 /**
3227  * @}
3228  */
3229 
3230 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
3231  * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
3232  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
3233  * power consumption.
3234  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
3235  * @note By default, all peripheral clocks are enabled during SLEEP mode.
3236  * @{
3237  */
3238 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
3239 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
3240 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
3241 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
3242 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
3243 
3244 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
3245 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
3246 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
3247 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
3248 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
3249 /**
3250  * @}
3251  */
3252 
3253 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
3254  * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
3255  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
3256  * power consumption.
3257  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
3258  * @note By default, all peripheral clocks are enabled during SLEEP mode.
3259  * @{
3260  */
3261 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
3262 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
3263 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
3264 
3265 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
3266 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
3267 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
3268 /**
3269  * @}
3270  */
3271 #endif /* STM32F401xC || STM32F401xE*/
3272 /*----------------------------------------------------------------------------*/
3273 
3274 /*-------------------------------- STM32F410xx -------------------------------*/
3275 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
3276 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
3277  * @brief Enables or disables the AHB1 peripheral clock.
3278  * @note After reset, the peripheral clock (used for registers read/write access)
3279  * is disabled and the application software has to enable this clock before
3280  * using it.
3281  * @{
3282  */
3283 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
3284  __IO uint32_t tmpreg = 0x00U; \
3285  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3286  /* Delay after an RCC peripheral clock enabling */ \
3287  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3288  UNUSED(tmpreg); \
3289  } while(0U)
3290 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
3291  __IO uint32_t tmpreg = 0x00U; \
3292  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
3293  /* Delay after an RCC peripheral clock enabling */ \
3294  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
3295  UNUSED(tmpreg); \
3296  } while(0U)
3297 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
3298 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
3299 /**
3300  * @}
3301  */
3302 
3303 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
3304  * @brief Get the enable or disable status of the AHB1 peripheral clock.
3305  * @note After reset, the peripheral clock (used for registers read/write access)
3306  * is disabled and the application software has to enable this clock before
3307  * using it.
3308  * @{
3309  */
3310 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
3311 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
3312 
3313 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
3314 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
3315 /**
3316  * @}
3317  */
3318 
3319 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
3320  * @brief Enable or disable the High Speed APB (APB1) peripheral clock.
3321  * @{
3322  */
3323 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
3324  __IO uint32_t tmpreg = 0x00U; \
3325  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
3326  /* Delay after an RCC peripheral clock enabling */ \
3327  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
3328  UNUSED(tmpreg); \
3329  } while(0U)
3330 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
3331  __IO uint32_t tmpreg = 0x00U; \
3332  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
3333  /* Delay after an RCC peripheral clock enabling */ \
3334  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
3335  UNUSED(tmpreg); \
3336  } while(0U)
3337 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
3338  __IO uint32_t tmpreg = 0x00U; \
3339  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
3340  /* Delay after an RCC peripheral clock enabling */ \
3341  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
3342  UNUSED(tmpreg); \
3343  } while(0U)
3344 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
3345  __IO uint32_t tmpreg = 0x00U; \
3346  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
3347  /* Delay after an RCC peripheral clock enabling */ \
3348  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
3349  UNUSED(tmpreg); \
3350  } while(0U)
3351 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
3352  __IO uint32_t tmpreg = 0x00U; \
3353  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
3354  /* Delay after an RCC peripheral clock enabling */ \
3355  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
3356  UNUSED(tmpreg); \
3357  } while(0U)
3358 
3359 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
3360 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
3361 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
3362 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
3363 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
3364 /**
3365  * @}
3366  */
3367 
3368 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
3369  * @brief Get the enable or disable status of the APB1 peripheral clock.
3370  * @note After reset, the peripheral clock (used for registers read/write access)
3371  * is disabled and the application software has to enable this clock before
3372  * using it.
3373  * @{
3374  */
3375 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
3376 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
3377 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
3378 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
3379 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
3380 
3381 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
3382 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
3383 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
3384 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
3385 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
3386 /**
3387  * @}
3388  */
3389 
3390 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
3391  * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
3392  * @{
3393  */
3394 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
3395  __IO uint32_t tmpreg = 0x00U; \
3396  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3397  /* Delay after an RCC peripheral clock enabling */ \
3398  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3399  UNUSED(tmpreg); \
3400  } while(0U)
3401 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
3402  __IO uint32_t tmpreg = 0x00U; \
3403  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
3404  /* Delay after an RCC peripheral clock enabling */ \
3405  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
3406  UNUSED(tmpreg); \
3407  } while(0U)
3408 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
3409 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
3410 /**
3411  * @}
3412  */
3413 
3414 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
3415  * @brief Get the enable or disable status of the APB2 peripheral clock.
3416  * @note After reset, the peripheral clock (used for registers read/write access)
3417  * is disabled and the application software has to enable this clock before
3418  * using it.
3419  * @{
3420  */
3421 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
3422 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
3423 
3424 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
3425 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
3426 /**
3427  * @}
3428  */
3429 
3430 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
3431  * @brief Force or release AHB1 peripheral reset.
3432  * @{
3433  */
3434 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
3435 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
3436 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
3437 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
3438 /**
3439  * @}
3440  */
3441 
3442 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
3443  * @brief Force or release AHB2 peripheral reset.
3444  * @{
3445  */
3446 #define __HAL_RCC_AHB2_FORCE_RESET()
3447 #define __HAL_RCC_AHB2_RELEASE_RESET()
3448 /**
3449  * @}
3450  */
3451 
3452 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
3453  * @brief Force or release AHB3 peripheral reset.
3454  * @{
3455  */
3456 #define __HAL_RCC_AHB3_FORCE_RESET()
3457 #define __HAL_RCC_AHB3_RELEASE_RESET()
3458 /**
3459  * @}
3460  */
3461 
3462 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
3463  * @brief Force or release APB1 peripheral reset.
3464  * @{
3465  */
3466 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
3467 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
3468 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
3469 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
3470 
3471 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
3472 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
3473 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
3474 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
3475 /**
3476  * @}
3477  */
3478 
3479 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
3480  * @brief Force or release APB2 peripheral reset.
3481  * @{
3482  */
3483 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
3484 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
3485 /**
3486  * @}
3487  */
3488 
3489 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
3490  * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
3491  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
3492  * power consumption.
3493  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
3494  * @note By default, all peripheral clocks are enabled during SLEEP mode.
3495  * @{
3496  */
3497 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
3498 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
3499 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
3500 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
3501 
3502 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
3503 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
3504 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
3505 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
3506 /**
3507  * @}
3508  */
3509 
3510 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
3511  * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
3512  * @{
3513  */
3514 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
3515 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
3516 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
3517 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
3518 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
3519 
3520 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
3521 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
3522 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
3523 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
3524 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
3525 /**
3526  * @}
3527  */
3528 
3529 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
3530  * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
3531  * @{
3532  */
3533 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
3534 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
3535 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
3536 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
3537 /**
3538  * @}
3539  */
3540 
3541 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
3542 /*----------------------------------------------------------------------------*/
3543 
3544 /*-------------------------------- STM32F411xx -------------------------------*/
3545 #if defined(STM32F411xE)
3546 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
3547  * @brief Enables or disables the AHB1 peripheral clock.
3548  * @note After reset, the peripheral clock (used for registers read/write access)
3549  * is disabled and the application software has to enable this clock before
3550  * using it.
3551  * @{
3552  */
3553 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
3554  __IO uint32_t tmpreg = 0x00U; \
3555  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3556  /* Delay after an RCC peripheral clock enabling */ \
3557  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3558  UNUSED(tmpreg); \
3559  } while(0U)
3560 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
3561  __IO uint32_t tmpreg = 0x00U; \
3562  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3563  /* Delay after an RCC peripheral clock enabling */ \
3564  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3565  UNUSED(tmpreg); \
3566  } while(0U)
3567 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
3568  __IO uint32_t tmpreg = 0x00U; \
3569  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3570  /* Delay after an RCC peripheral clock enabling */ \
3571  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3572  UNUSED(tmpreg); \
3573  } while(0U)
3574 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
3575  __IO uint32_t tmpreg = 0x00U; \
3576  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3577  /* Delay after an RCC peripheral clock enabling */ \
3578  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3579  UNUSED(tmpreg); \
3580  } while(0U)
3581 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
3582 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
3583 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
3584 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
3585 /**
3586  * @}
3587  */
3588 
3589 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
3590  * @brief Get the enable or disable status of the AHB1 peripheral clock.
3591  * @note After reset, the peripheral clock (used for registers read/write access)
3592  * is disabled and the application software has to enable this clock before
3593  * using it.
3594  * @{
3595  */
3596 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
3597 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
3598 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
3599 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
3600 
3601 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
3602 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
3603 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
3604 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
3605 /**
3606  * @}
3607  */
3608 
3609 /** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
3610  * @brief Enable or disable the AHB2 peripheral clock.
3611  * @note After reset, the peripheral clock (used for registers read/write access)
3612  * is disabled and the application software has to enable this clock before
3613  * using it.
3614  * @{
3615  */
3616 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
3617  __HAL_RCC_SYSCFG_CLK_ENABLE();\
3618  }while(0U)
3619 
3620 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
3621 /**
3622  * @}
3623  */
3624 
3625 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
3626  * @brief Get the enable or disable status of the AHB2 peripheral clock.
3627  * @note After reset, the peripheral clock (used for registers read/write access)
3628  * is disabled and the application software has to enable this clock before
3629  * using it.
3630  * @{
3631  */
3632 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
3633 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
3634 /**
3635  * @}
3636  */
3637 
3638 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
3639  * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
3640  * @note After reset, the peripheral clock (used for registers read/write access)
3641  * is disabled and the application software has to enable this clock before
3642  * using it.
3643  * @{
3644  */
3645 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
3646  __IO uint32_t tmpreg = 0x00U; \
3647  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
3648  /* Delay after an RCC peripheral clock enabling */ \
3649  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
3650  UNUSED(tmpreg); \
3651  } while(0U)
3652 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
3653  __IO uint32_t tmpreg = 0x00U; \
3654  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
3655  /* Delay after an RCC peripheral clock enabling */ \
3656  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
3657  UNUSED(tmpreg); \
3658  } while(0U)
3659 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
3660  __IO uint32_t tmpreg = 0x00U; \
3661  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
3662  /* Delay after an RCC peripheral clock enabling */ \
3663  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
3664  UNUSED(tmpreg); \
3665  } while(0U)
3666 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
3667  __IO uint32_t tmpreg = 0x00U; \
3668  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
3669  /* Delay after an RCC peripheral clock enabling */ \
3670  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
3671  UNUSED(tmpreg); \
3672  } while(0U)
3673 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
3674  __IO uint32_t tmpreg = 0x00U; \
3675  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
3676  /* Delay after an RCC peripheral clock enabling */ \
3677  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
3678  UNUSED(tmpreg); \
3679  } while(0U)
3680 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
3681 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
3682 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
3683 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
3684 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
3685 /**
3686  * @}
3687  */
3688 
3689 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
3690  * @brief Get the enable or disable status of the APB1 peripheral clock.
3691  * @note After reset, the peripheral clock (used for registers read/write access)
3692  * is disabled and the application software has to enable this clock before
3693  * using it.
3694  * @{
3695  */
3696 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
3697 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
3698 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
3699 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
3700 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
3701 
3702 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
3703 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
3704 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
3705 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
3706 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
3707 /**
3708  * @}
3709  */
3710 
3711 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
3712  * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
3713  * @{
3714  */
3715 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
3716  __IO uint32_t tmpreg = 0x00U; \
3717  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3718  /* Delay after an RCC peripheral clock enabling */ \
3719  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3720  UNUSED(tmpreg); \
3721  } while(0U)
3722 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
3723  __IO uint32_t tmpreg = 0x00U; \
3724  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
3725  /* Delay after an RCC peripheral clock enabling */ \
3726  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
3727  UNUSED(tmpreg); \
3728  } while(0U)
3729 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
3730  __IO uint32_t tmpreg = 0x00U; \
3731  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3732  /* Delay after an RCC peripheral clock enabling */ \
3733  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3734  UNUSED(tmpreg); \
3735  } while(0U)
3736 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
3737  __IO uint32_t tmpreg = 0x00U; \
3738  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3739  /* Delay after an RCC peripheral clock enabling */ \
3740  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3741  UNUSED(tmpreg); \
3742  } while(0U)
3743 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
3744 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
3745 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
3746 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
3747 /**
3748  * @}
3749  */
3750 
3751 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
3752  * @brief Get the enable or disable status of the APB2 peripheral clock.
3753  * @note After reset, the peripheral clock (used for registers read/write access)
3754  * is disabled and the application software has to enable this clock before
3755  * using it.
3756  * @{
3757  */
3758 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
3759 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
3760 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
3761 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
3762 
3763 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
3764 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
3765 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
3766 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
3767 /**
3768  * @}
3769  */
3770 
3771 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
3772  * @brief Force or release AHB1 peripheral reset.
3773  * @{
3774  */
3775 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
3776 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
3777 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
3778 
3779 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
3780 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
3781 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
3782 /**
3783  * @}
3784  */
3785 
3786 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
3787  * @brief Force or release AHB2 peripheral reset.
3788  * @{
3789  */
3790 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
3791 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
3792 
3793 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
3794 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
3795 /**
3796  * @}
3797  */
3798 
3799 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
3800  * @brief Force or release AHB3 peripheral reset.
3801  * @{
3802  */
3803 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
3804 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
3805 /**
3806  * @}
3807  */
3808 
3809 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
3810  * @brief Force or release APB1 peripheral reset.
3811  * @{
3812  */
3813 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
3814 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
3815 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
3816 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
3817 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
3818 
3819 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
3820 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
3821 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
3822 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
3823 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
3824 /**
3825  * @}
3826  */
3827 
3828 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
3829  * @brief Force or release APB2 peripheral reset.
3830  * @{
3831  */
3832 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
3833 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
3834 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
3835 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
3836 
3837 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
3838 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
3839 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
3840 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
3841 /**
3842  * @}
3843  */
3844 
3845 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
3846  * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
3847  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
3848  * power consumption.
3849  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
3850  * @note By default, all peripheral clocks are enabled during SLEEP mode.
3851  * @{
3852  */
3853 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
3854 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
3855 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
3856 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
3857 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
3858 
3859 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
3860 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
3861 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
3862 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
3863 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
3864 /**
3865  * @}
3866  */
3867 
3868 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
3869  * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
3870  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
3871  * power consumption.
3872  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
3873  * @note By default, all peripheral clocks are enabled during SLEEP mode.
3874  * @{
3875  */
3876 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
3877 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
3878 /**
3879  * @}
3880  */
3881 
3882 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
3883  * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
3884  * @{
3885  */
3886 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
3887 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
3888 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
3889 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
3890 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
3891 
3892 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
3893 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
3894 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
3895 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
3896 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
3897 /**
3898  * @}
3899  */
3900 
3901 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
3902  * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
3903  * @{
3904  */
3905 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
3906 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
3907 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
3908 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
3909 
3910 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
3911 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
3912 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
3913 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
3914 /**
3915  * @}
3916  */
3917 #endif /* STM32F411xE */
3918 /*----------------------------------------------------------------------------*/
3919 
3920 /*---------------------------------- STM32F446xx -----------------------------*/
3921 #if defined(STM32F446xx)
3922 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
3923  * @brief Enables or disables the AHB1 peripheral clock.
3924  * @note After reset, the peripheral clock (used for registers read/write access)
3925  * is disabled and the application software has to enable this clock before
3926  * using it.
3927  * @{
3928  */
3929 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
3930  __IO uint32_t tmpreg = 0x00U; \
3931  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
3932  /* Delay after an RCC peripheral clock enabling */ \
3933  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
3934  UNUSED(tmpreg); \
3935  } while(0U)
3936 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
3937  __IO uint32_t tmpreg = 0x00U; \
3938  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3939  /* Delay after an RCC peripheral clock enabling */ \
3940  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3941  UNUSED(tmpreg); \
3942  } while(0U)
3943 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
3944  __IO uint32_t tmpreg = 0x00U; \
3945  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3946  /* Delay after an RCC peripheral clock enabling */ \
3947  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3948  UNUSED(tmpreg); \
3949  } while(0U)
3950 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
3951  __IO uint32_t tmpreg = 0x00U; \
3952  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3953  /* Delay after an RCC peripheral clock enabling */ \
3954  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3955  UNUSED(tmpreg); \
3956  } while(0U)
3957 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
3958  __IO uint32_t tmpreg = 0x00U; \
3959  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3960  /* Delay after an RCC peripheral clock enabling */ \
3961  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3962  UNUSED(tmpreg); \
3963  } while(0U)
3964 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
3965  __IO uint32_t tmpreg = 0x00U; \
3966  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
3967  /* Delay after an RCC peripheral clock enabling */ \
3968  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
3969  UNUSED(tmpreg); \
3970  } while(0U)
3971 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
3972  __IO uint32_t tmpreg = 0x00U; \
3973  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
3974  /* Delay after an RCC peripheral clock enabling */ \
3975  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
3976  UNUSED(tmpreg); \
3977  } while(0U)
3978 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
3979  __IO uint32_t tmpreg = 0x00U; \
3980  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
3981  /* Delay after an RCC peripheral clock enabling */ \
3982  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
3983  UNUSED(tmpreg); \
3984  } while(0U)
3985 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
3986  __IO uint32_t tmpreg = 0x00U; \
3987  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
3988  /* Delay after an RCC peripheral clock enabling */ \
3989  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
3990  UNUSED(tmpreg); \
3991  } while(0U)
3992 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
3993 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
3994 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
3995 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
3996 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
3997 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
3998 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
3999 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
4000 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
4001 /**
4002  * @}
4003  */
4004 
4005 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
4006  * @brief Get the enable or disable status of the AHB1 peripheral clock.
4007  * @note After reset, the peripheral clock (used for registers read/write access)
4008  * is disabled and the application software has to enable this clock before
4009  * using it.
4010  * @{
4011  */
4012 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
4013 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
4014 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
4015 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
4016 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
4017 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
4018 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
4019 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
4020 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
4021 
4022 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
4023 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
4024 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
4025 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
4026 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
4027 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
4028 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
4029 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
4030 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
4031 /**
4032  * @}
4033  */
4034 
4035 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
4036  * @brief Enable or disable the AHB2 peripheral clock.
4037  * @note After reset, the peripheral clock (used for registers read/write access)
4038  * is disabled and the application software has to enable this clock before
4039  * using it.
4040  * @{
4041  */
4042 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
4043  __IO uint32_t tmpreg = 0x00U; \
4044  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
4045  /* Delay after an RCC peripheral clock enabling */ \
4046  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
4047  UNUSED(tmpreg); \
4048  } while(0U)
4049 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
4050 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
4051  __HAL_RCC_SYSCFG_CLK_ENABLE();\
4052  }while(0U)
4053 
4054 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
4055 
4056 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
4057  __IO uint32_t tmpreg = 0x00U; \
4058  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
4059  /* Delay after an RCC peripheral clock enabling */ \
4060  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
4061  UNUSED(tmpreg); \
4062  } while(0U)
4063 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
4064 /**
4065  * @}
4066  */
4067 
4068 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
4069  * @brief Get the enable or disable status of the AHB2 peripheral clock.
4070  * @note After reset, the peripheral clock (used for registers read/write access)
4071  * is disabled and the application software has to enable this clock before
4072  * using it.
4073  * @{
4074  */
4075 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
4076 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
4077 
4078 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
4079 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
4080 
4081 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
4082 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
4083 /**
4084  * @}
4085  */
4086 
4087 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
4088  * @brief Enables or disables the AHB3 peripheral clock.
4089  * @note After reset, the peripheral clock (used for registers read/write access)
4090  * is disabled and the application software has to enable this clock before
4091  * using it.
4092  * @{
4093  */
4094 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
4095  __IO uint32_t tmpreg = 0x00U; \
4096  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
4097  /* Delay after an RCC peripheral clock enabling */ \
4098  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
4099  UNUSED(tmpreg); \
4100  } while(0U)
4101 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
4102  __IO uint32_t tmpreg = 0x00U; \
4103  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4104  /* Delay after an RCC peripheral clock enabling */ \
4105  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4106  UNUSED(tmpreg); \
4107  } while(0U)
4108 
4109 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
4110 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
4111 /**
4112  * @}
4113  */
4114 
4115 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
4116  * @brief Get the enable or disable status of the AHB3 peripheral clock.
4117  * @note After reset, the peripheral clock (used for registers read/write access)
4118  * is disabled and the application software has to enable this clock before
4119  * using it.
4120  * @{
4121  */
4122 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
4123 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
4124 
4125 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
4126 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
4127 /**
4128  * @}
4129  */
4130 
4131 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
4132  * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
4133  * @note After reset, the peripheral clock (used for registers read/write access)
4134  * is disabled and the application software has to enable this clock before
4135  * using it.
4136  * @{
4137  */
4138 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
4139  __IO uint32_t tmpreg = 0x00U; \
4140  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4141  /* Delay after an RCC peripheral clock enabling */ \
4142  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4143  UNUSED(tmpreg); \
4144  } while(0U)
4145 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
4146  __IO uint32_t tmpreg = 0x00U; \
4147  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4148  /* Delay after an RCC peripheral clock enabling */ \
4149  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4150  UNUSED(tmpreg); \
4151  } while(0U)
4152 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
4153  __IO uint32_t tmpreg = 0x00U; \
4154  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4155  /* Delay after an RCC peripheral clock enabling */ \
4156  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4157  UNUSED(tmpreg); \
4158  } while(0U)
4159 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
4160  __IO uint32_t tmpreg = 0x00U; \
4161  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4162  /* Delay after an RCC peripheral clock enabling */ \
4163  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4164  UNUSED(tmpreg); \
4165  } while(0U)
4166 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
4167  __IO uint32_t tmpreg = 0x00U; \
4168  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4169  /* Delay after an RCC peripheral clock enabling */ \
4170  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4171  UNUSED(tmpreg); \
4172  } while(0U)
4173 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
4174  __IO uint32_t tmpreg = 0x00U; \
4175  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
4176  /* Delay after an RCC peripheral clock enabling */ \
4177  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
4178  UNUSED(tmpreg); \
4179  } while(0U)
4180 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
4181  __IO uint32_t tmpreg = 0x00U; \
4182  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4183  /* Delay after an RCC peripheral clock enabling */ \
4184  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4185  UNUSED(tmpreg); \
4186  } while(0U)
4187 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
4188  __IO uint32_t tmpreg = 0x00U; \
4189  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
4190  /* Delay after an RCC peripheral clock enabling */ \
4191  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
4192  UNUSED(tmpreg); \
4193  } while(0U)
4194 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
4195  __IO uint32_t tmpreg = 0x00U; \
4196  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
4197  /* Delay after an RCC peripheral clock enabling */ \
4198  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
4199  UNUSED(tmpreg); \
4200  } while(0U)
4201 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
4202  __IO uint32_t tmpreg = 0x00U; \
4203  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
4204  /* Delay after an RCC peripheral clock enabling */ \
4205  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
4206  UNUSED(tmpreg); \
4207  } while(0U)
4208 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
4209  __IO uint32_t tmpreg = 0x00U; \
4210  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
4211  /* Delay after an RCC peripheral clock enabling */ \
4212  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
4213  UNUSED(tmpreg); \
4214  } while(0U)
4215 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
4216  __IO uint32_t tmpreg = 0x00U; \
4217  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
4218  /* Delay after an RCC peripheral clock enabling */ \
4219  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
4220  UNUSED(tmpreg); \
4221  } while(0U)
4222 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
4223  __IO uint32_t tmpreg = 0x00U; \
4224  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
4225  /* Delay after an RCC peripheral clock enabling */ \
4226  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
4227  UNUSED(tmpreg); \
4228  } while(0U)
4229 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
4230  __IO uint32_t tmpreg = 0x00U; \
4231  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
4232  /* Delay after an RCC peripheral clock enabling */ \
4233  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
4234  UNUSED(tmpreg); \
4235  } while(0U)
4236 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
4237  __IO uint32_t tmpreg = 0x00U; \
4238  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
4239  /* Delay after an RCC peripheral clock enabling */ \
4240  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
4241  UNUSED(tmpreg); \
4242  } while(0U)
4243 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
4244  __IO uint32_t tmpreg = 0x00U; \
4245  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
4246  /* Delay after an RCC peripheral clock enabling */ \
4247  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
4248  UNUSED(tmpreg); \
4249  } while(0U)
4250 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
4251  __IO uint32_t tmpreg = 0x00U; \
4252  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
4253  /* Delay after an RCC peripheral clock enabling */ \
4254  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
4255  UNUSED(tmpreg); \
4256  } while(0U)
4257 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
4258  __IO uint32_t tmpreg = 0x00U; \
4259  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
4260  /* Delay after an RCC peripheral clock enabling */ \
4261  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
4262  UNUSED(tmpreg); \
4263  } while(0U)
4264 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
4265  __IO uint32_t tmpreg = 0x00U; \
4266  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
4267  /* Delay after an RCC peripheral clock enabling */ \
4268  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
4269  UNUSED(tmpreg); \
4270  } while(0U)
4271 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
4272 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
4273 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
4274 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
4275 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
4276 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
4277 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
4278 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
4279 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
4280 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
4281 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
4282 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
4283 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
4284 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
4285 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
4286 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
4287 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
4288 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
4289 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
4290 /**
4291  * @}
4292  */
4293 
4294 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
4295  * @brief Get the enable or disable status of the APB1 peripheral clock.
4296  * @note After reset, the peripheral clock (used for registers read/write access)
4297  * is disabled and the application software has to enable this clock before
4298  * using it.
4299  * @{
4300  */
4301 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
4302 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
4303 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
4304 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
4305 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
4306 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
4307 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
4308 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
4309 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
4310 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
4311 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
4312 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
4313 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
4314 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
4315 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
4316 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
4317 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
4318 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
4319 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
4320 
4321 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
4322 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
4323 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
4324 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
4325 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
4326 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
4327 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
4328 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
4329 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
4330 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
4331 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
4332 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
4333 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
4334 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
4335 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
4336 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
4337 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
4338 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
4339 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
4340 /**
4341  * @}
4342  */
4343 
4344 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
4345  * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
4346  * @note After reset, the peripheral clock (used for registers read/write access)
4347  * is disabled and the application software has to enable this clock before
4348  * using it.
4349  * @{
4350  */
4351 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
4352  __IO uint32_t tmpreg = 0x00U; \
4353  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
4354  /* Delay after an RCC peripheral clock enabling */ \
4355  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
4356  UNUSED(tmpreg); \
4357  } while(0U)
4358 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
4359  __IO uint32_t tmpreg = 0x00U; \
4360  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
4361  /* Delay after an RCC peripheral clock enabling */ \
4362  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
4363  UNUSED(tmpreg); \
4364  } while(0U)
4365 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
4366  __IO uint32_t tmpreg = 0x00U; \
4367  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
4368  /* Delay after an RCC peripheral clock enabling */ \
4369  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
4370  UNUSED(tmpreg); \
4371  } while(0U)
4372 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
4373  __IO uint32_t tmpreg = 0x00U; \
4374  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
4375  /* Delay after an RCC peripheral clock enabling */ \
4376  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
4377  UNUSED(tmpreg); \
4378  } while(0U)
4379 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
4380  __IO uint32_t tmpreg = 0x00U; \
4381  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
4382  /* Delay after an RCC peripheral clock enabling */ \
4383  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
4384  UNUSED(tmpreg); \
4385  } while(0U)
4386 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
4387  __IO uint32_t tmpreg = 0x00U; \
4388  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
4389  /* Delay after an RCC peripheral clock enabling */ \
4390  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
4391  UNUSED(tmpreg); \
4392  } while(0U)
4393 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
4394  __IO uint32_t tmpreg = 0x00U; \
4395  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
4396  /* Delay after an RCC peripheral clock enabling */ \
4397  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
4398  UNUSED(tmpreg); \
4399  } while(0U)
4400 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
4401  __IO uint32_t tmpreg = 0x00U; \
4402  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
4403  /* Delay after an RCC peripheral clock enabling */ \
4404  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
4405  UNUSED(tmpreg); \
4406  } while(0U)
4407 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
4408 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
4409 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
4410 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
4411 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
4412 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
4413 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
4414 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
4415 /**
4416  * @}
4417  */
4418 
4419 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
4420  * @brief Get the enable or disable status of the APB2 peripheral clock.
4421  * @note After reset, the peripheral clock (used for registers read/write access)
4422  * is disabled and the application software has to enable this clock before
4423  * using it.
4424  * @{
4425  */
4426 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
4427 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
4428 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
4429 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
4430 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
4431 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
4432 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
4433 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
4434 
4435 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
4436 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
4437 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
4438 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
4439 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
4440 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
4441 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
4442 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
4443 /**
4444  * @}
4445  */
4446 
4447 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
4448  * @brief Force or release AHB1 peripheral reset.
4449  * @{
4450  */
4451 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
4452 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
4453 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
4454 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
4455 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
4456 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
4457 
4458 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
4459 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
4460 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
4461 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
4462 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
4463 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
4464 /**
4465  * @}
4466  */
4467 
4468 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
4469  * @brief Force or release AHB2 peripheral reset.
4470  * @{
4471  */
4472 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
4473 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
4474 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
4475 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
4476 
4477 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
4478 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
4479 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
4480 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
4481 /**
4482  * @}
4483  */
4484 
4485 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
4486  * @brief Force or release AHB3 peripheral reset.
4487  * @{
4488  */
4489 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
4490 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
4491 
4492 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
4493 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
4494 
4495 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
4496 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
4497 /**
4498  * @}
4499  */
4500 
4501 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
4502  * @brief Force or release APB1 peripheral reset.
4503  * @{
4504  */
4505 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
4506 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
4507 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
4508 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
4509 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
4510 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
4511 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
4512 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
4513 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
4514 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
4515 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
4516 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
4517 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
4518 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
4519 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
4520 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
4521 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
4522 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
4523 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
4524 
4525 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
4526 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
4527 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
4528 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
4529 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
4530 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
4531 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
4532 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
4533 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
4534 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
4535 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
4536 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
4537 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
4538 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
4539 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
4540 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
4541 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
4542 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
4543 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
4544 /**
4545  * @}
4546  */
4547 
4548 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
4549  * @brief Force or release APB2 peripheral reset.
4550  * @{
4551  */
4552 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
4553 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
4554 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
4555 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
4556 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
4557 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
4558 
4559 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
4560 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
4561 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
4562 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
4563 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
4564 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
4565 /**
4566  * @}
4567  */
4568 
4569 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
4570  * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
4571  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
4572  * power consumption.
4573  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
4574  * @note By default, all peripheral clocks are enabled during SLEEP mode.
4575  * @{
4576  */
4577 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
4578 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
4579 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
4580 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
4581 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
4582 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
4583 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
4584 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
4585 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
4586 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
4587 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
4588 
4589 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
4590 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
4591 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
4592 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
4593 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
4594 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
4595 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
4596 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
4597 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
4598 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
4599 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
4600 /**
4601  * @}
4602  */
4603 
4604 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
4605  * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
4606  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
4607  * power consumption.
4608  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
4609  * @note By default, all peripheral clocks are enabled during SLEEP mode.
4610  * @{
4611  */
4612 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
4613 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
4614 
4615 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
4616 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
4617 
4618 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
4619 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
4620 /**
4621  * @}
4622  */
4623 
4624 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
4625  * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
4626  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
4627  * power consumption.
4628  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
4629  * @note By default, all peripheral clocks are enabled during SLEEP mode.
4630  * @{
4631  */
4632 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
4633 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
4634 
4635 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
4636 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
4637 /**
4638  * @}
4639  */
4640 
4641 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
4642  * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
4643  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
4644  * power consumption.
4645  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
4646  * @note By default, all peripheral clocks are enabled during SLEEP mode.
4647  * @{
4648  */
4649 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
4650 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
4651 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
4652 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
4653 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
4654 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
4655 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
4656 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
4657 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
4658 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
4659 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
4660 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
4661 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
4662 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
4663 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
4664 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
4665 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
4666 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
4667 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
4668 
4669 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
4670 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
4671 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
4672 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
4673 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
4674 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
4675 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
4676 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
4677 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
4678 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
4679 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
4680 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
4681 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
4682 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
4683 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
4684 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
4685 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
4686 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
4687 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
4688 /**
4689  * @}
4690  */
4691 
4692 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
4693  * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
4694  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
4695  * power consumption.
4696  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
4697  * @note By default, all peripheral clocks are enabled during SLEEP mode.
4698  * @{
4699  */
4700 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
4701 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
4702 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
4703 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
4704 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
4705 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
4706 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
4707 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
4708 
4709 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
4710 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
4711 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
4712 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
4713 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
4714 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
4715 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
4716 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
4717 /**
4718  * @}
4719  */
4720 
4721 #endif /* STM32F446xx */
4722 /*----------------------------------------------------------------------------*/
4723 
4724 /*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/
4725 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
4726 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
4727  * @brief Enables or disables the AHB1 peripheral clock.
4728  * @note After reset, the peripheral clock (used for registers read/write access)
4729  * is disabled and the application software has to enable this clock before
4730  * using it.
4731  * @{
4732  */
4733 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
4734  __IO uint32_t tmpreg = 0x00U; \
4735  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
4736  /* Delay after an RCC peripheral clock enabling */ \
4737  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
4738  UNUSED(tmpreg); \
4739  } while(0U)
4740 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
4741  __IO uint32_t tmpreg = 0x00U; \
4742  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
4743  /* Delay after an RCC peripheral clock enabling */ \
4744  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
4745  UNUSED(tmpreg); \
4746  } while(0U)
4747 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
4748  __IO uint32_t tmpreg = 0x00U; \
4749  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
4750  /* Delay after an RCC peripheral clock enabling */ \
4751  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
4752  UNUSED(tmpreg); \
4753  } while(0U)
4754 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
4755  __IO uint32_t tmpreg = 0x00U; \
4756  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
4757  /* Delay after an RCC peripheral clock enabling */ \
4758  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
4759  UNUSED(tmpreg); \
4760  } while(0U)
4761 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
4762  __IO uint32_t tmpreg = 0x00U; \
4763  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
4764  /* Delay after an RCC peripheral clock enabling */ \
4765  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
4766  UNUSED(tmpreg); \
4767  } while(0U)
4768 
4769 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
4770 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
4771 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
4772 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
4773 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
4774 /**
4775  * @}
4776  */
4777 
4778 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
4779  * @brief Get the enable or disable status of the AHB1 peripheral clock.
4780  * @note After reset, the peripheral clock (used for registers read/write access)
4781  * is disabled and the application software has to enable this clock before
4782  * using it.
4783  * @{
4784  */
4785 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
4786 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
4787 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
4788 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
4789 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
4790 
4791 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
4792 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
4793 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
4794 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
4795 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
4796 /**
4797  * @}
4798  */
4799 
4800 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
4801  * @brief Enable or disable the AHB2 peripheral clock.
4802  * @note After reset, the peripheral clock (used for registers read/write access)
4803  * is disabled and the application software has to enable this clock before
4804  * using it.
4805  * @{
4806  */
4807 #if defined(STM32F423xx)
4808 #define __HAL_RCC_AES_CLK_ENABLE() do { \
4809  __IO uint32_t tmpreg = 0x00U; \
4810  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
4811  /* Delay after an RCC peripheral clock enabling */ \
4812  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
4813  UNUSED(tmpreg); \
4814  } while(0U)
4815 
4816 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
4817 #endif /* STM32F423xx */
4818 
4819 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
4820  __IO uint32_t tmpreg = 0x00U; \
4821  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
4822  /* Delay after an RCC peripheral clock enabling */ \
4823  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
4824  UNUSED(tmpreg); \
4825  } while(0U)
4826 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
4827 
4828 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
4829  __HAL_RCC_SYSCFG_CLK_ENABLE();\
4830  }while(0U)
4831 
4832 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
4833 /**
4834  * @}
4835  */
4836 
4837 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
4838  * @brief Get the enable or disable status of the AHB2 peripheral clock.
4839  * @note After reset, the peripheral clock (used for registers read/write access)
4840  * is disabled and the application software has to enable this clock before
4841  * using it.
4842  * @{
4843  */
4844 #if defined(STM32F423xx)
4845 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
4846 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
4847 #endif /* STM32F423xx */
4848 
4849 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
4850 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
4851 
4852 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
4853 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
4854 /**
4855  * @}
4856  */
4857 
4858 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
4859  * @brief Enables or disables the AHB3 peripheral clock.
4860  * @note After reset, the peripheral clock (used for registers read/write access)
4861  * is disabled and the application software has to enable this clock before
4862  * using it.
4863  * @{
4864  */
4865 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
4866 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
4867  __IO uint32_t tmpreg = 0x00U; \
4868  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
4869  /* Delay after an RCC peripheral clock enabling */ \
4870  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
4871  UNUSED(tmpreg); \
4872  } while(0U)
4873 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
4874  __IO uint32_t tmpreg = 0x00U; \
4875  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4876  /* Delay after an RCC peripheral clock enabling */ \
4877  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4878  UNUSED(tmpreg); \
4879  } while(0U)
4880 
4881 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
4882 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
4883 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
4884 /**
4885  * @}
4886  */
4887 
4888 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
4889  * @brief Get the enable or disable status of the AHB3 peripheral clock.
4890  * @note After reset, the peripheral clock (used for registers read/write access)
4891  * is disabled and the application software has to enable this clock before
4892  * using it.
4893  * @{
4894  */
4895 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
4896 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
4897 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
4898 
4899 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
4900 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
4901 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
4902 
4903 /**
4904  * @}
4905  */
4906 
4907 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
4908  * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
4909  * @note After reset, the peripheral clock (used for registers read/write access)
4910  * is disabled and the application software has to enable this clock before
4911  * using it.
4912  * @{
4913  */
4914 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
4915  __IO uint32_t tmpreg = 0x00U; \
4916  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4917  /* Delay after an RCC peripheral clock enabling */ \
4918  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4919  UNUSED(tmpreg); \
4920  } while(0U)
4921 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
4922  __IO uint32_t tmpreg = 0x00U; \
4923  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4924  /* Delay after an RCC peripheral clock enabling */ \
4925  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4926  UNUSED(tmpreg); \
4927  } while(0U)
4928 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
4929  __IO uint32_t tmpreg = 0x00U; \
4930  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4931  /* Delay after an RCC peripheral clock enabling */ \
4932  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4933  UNUSED(tmpreg); \
4934  } while(0U)
4935 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
4936  __IO uint32_t tmpreg = 0x00U; \
4937  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4938  /* Delay after an RCC peripheral clock enabling */ \
4939  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4940  UNUSED(tmpreg); \
4941  } while(0U)
4942 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
4943  __IO uint32_t tmpreg = 0x00U; \
4944  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4945  /* Delay after an RCC peripheral clock enabling */ \
4946  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4947  UNUSED(tmpreg); \
4948  } while(0U)
4949 #if defined(STM32F413xx) || defined(STM32F423xx)
4950 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
4951  __IO uint32_t tmpreg = 0x00U; \
4952  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
4953  /* Delay after an RCC peripheral clock enabling */ \
4954  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
4955  UNUSED(tmpreg); \
4956  } while(0U)
4957 #endif /* STM32F413xx || STM32F423xx */
4958 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
4959  __IO uint32_t tmpreg = 0x00U; \
4960  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
4961  /* Delay after an RCC peripheral clock enabling */ \
4962  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
4963  UNUSED(tmpreg); \
4964  } while(0U)
4965 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
4966 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
4967  __IO uint32_t tmpreg = 0x00U; \
4968  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4969  /* Delay after an RCC peripheral clock enabling */ \
4970  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4971  UNUSED(tmpreg); \
4972  } while(0U)
4973 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
4974 
4975 #if defined(STM32F413xx) || defined(STM32F423xx)
4976 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
4977  __IO uint32_t tmpreg = 0x00U; \
4978  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
4979  /* Delay after an RCC peripheral clock enabling */ \
4980  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
4981  UNUSED(tmpreg); \
4982  } while(0U)
4983 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
4984  __IO uint32_t tmpreg = 0x00U; \
4985  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
4986  /* Delay after an RCC peripheral clock enabling */ \
4987  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
4988  UNUSED(tmpreg); \
4989  } while(0U)
4990 #endif /* STM32F413xx || STM32F423xx */
4991 
4992 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
4993  __IO uint32_t tmpreg = 0x00U; \
4994  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
4995  /* Delay after an RCC peripheral clock enabling */ \
4996  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
4997  UNUSED(tmpreg); \
4998  } while(0U)
4999 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
5000  __IO uint32_t tmpreg = 0x00U; \
5001  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
5002  /* Delay after an RCC peripheral clock enabling */ \
5003  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
5004  UNUSED(tmpreg); \
5005  } while(0U)
5006 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
5007  __IO uint32_t tmpreg = 0x00U; \
5008  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
5009  /* Delay after an RCC peripheral clock enabling */ \
5010  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
5011  UNUSED(tmpreg); \
5012  } while(0U)
5013 #if defined(STM32F413xx) || defined(STM32F423xx)
5014 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \
5015  __IO uint32_t tmpreg = 0x00U; \
5016  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
5017  /* Delay after an RCC peripheral clock enabling */ \
5018  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
5019  UNUSED(tmpreg); \
5020  } while(0U)
5021 #endif /* STM32F413xx || STM32F423xx */
5022 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
5023  __IO uint32_t tmpreg = 0x00U; \
5024  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
5025  /* Delay after an RCC peripheral clock enabling */ \
5026  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
5027  UNUSED(tmpreg); \
5028  } while(0U)
5029 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
5030  __IO uint32_t tmpreg = 0x00U; \
5031  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
5032  /* Delay after an RCC peripheral clock enabling */ \
5033  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
5034  UNUSED(tmpreg); \
5035  } while(0U)
5036 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
5037  __IO uint32_t tmpreg = 0x00U; \
5038  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
5039  /* Delay after an RCC peripheral clock enabling */ \
5040  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
5041  UNUSED(tmpreg); \
5042  } while(0U)
5043 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
5044  __IO uint32_t tmpreg = 0x00U; \
5045  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
5046  /* Delay after an RCC peripheral clock enabling */ \
5047  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
5048  UNUSED(tmpreg); \
5049  } while(0U)
5050 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
5051  __IO uint32_t tmpreg = 0x00U; \
5052  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
5053  /* Delay after an RCC peripheral clock enabling */ \
5054  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
5055  UNUSED(tmpreg); \
5056  } while(0U)
5057 #if defined(STM32F413xx) || defined(STM32F423xx)
5058 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
5059  __IO uint32_t tmpreg = 0x00U; \
5060  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
5061  /* Delay after an RCC peripheral clock enabling */ \
5062  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
5063  UNUSED(tmpreg); \
5064  } while(0U)
5065 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
5066  __IO uint32_t tmpreg = 0x00U; \
5067  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
5068  /* Delay after an RCC peripheral clock enabling */ \
5069  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
5070  UNUSED(tmpreg); \
5071  } while(0U)
5072 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
5073  __IO uint32_t tmpreg = 0x00U; \
5074  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
5075  /* Delay after an RCC peripheral clock enabling */ \
5076  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
5077  UNUSED(tmpreg); \
5078  } while(0U)
5079 #endif /* STM32F413xx || STM32F423xx */
5080 
5081 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
5082 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
5083 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
5084 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
5085 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
5086 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
5087 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
5088 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
5089 #if defined(STM32F413xx) || defined(STM32F423xx)
5090 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
5091 #endif /* STM32F413xx || STM32F423xx */
5092 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
5093 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
5094 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5095 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
5096 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5097 #if defined(STM32F413xx) || defined(STM32F423xx)
5098 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
5099 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
5100 #endif /* STM32F413xx || STM32F423xx */
5101 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
5102 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
5103 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
5104 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
5105 #if defined(STM32F413xx) || defined(STM32F423xx)
5106 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
5107 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
5108 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
5109 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
5110 #endif /* STM32F413xx || STM32F423xx */
5111 
5112 /**
5113  * @}
5114  */
5115 
5116 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
5117  * @brief Get the enable or disable status of the APB1 peripheral clock.
5118  * @note After reset, the peripheral clock (used for registers read/write access)
5119  * is disabled and the application software has to enable this clock before
5120  * using it.
5121  * @{
5122  */
5123 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
5124 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
5125 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
5126 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
5127 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
5128 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
5129 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
5130 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
5131 #if defined(STM32F413xx) || defined(STM32F423xx)
5132 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
5133 #endif /* STM32F413xx || STM32F423xx */
5134 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
5135 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
5136 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5137 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
5138 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
5139 #if defined(STM32F413xx) || defined(STM32F423xx)
5140 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
5141 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
5142 #endif /* STM32F413xx || STM32F423xx */
5143 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
5144 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
5145 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
5146 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
5147 #if defined(STM32F413xx) || defined(STM32F423xx)
5148 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
5149 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
5150 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
5151 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
5152 #endif /* STM32F413xx || STM32F423xx */
5153 
5154 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
5155 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
5156 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
5157 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
5158 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
5159 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
5160 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
5161 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
5162 #if defined(STM32F413xx) || defined(STM32F423xx)
5163 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
5164 #endif /* STM32F413xx || STM32F423xx */
5165 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
5166 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
5167 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5168 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
5169 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
5170 #if defined(STM32F413xx) || defined(STM32F423xx)
5171 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
5172 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
5173 #endif /* STM32F413xx || STM32F423xx */
5174 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
5175 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
5176 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
5177 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
5178 #if defined(STM32F413xx) || defined(STM32F423xx)
5179 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
5180 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
5181 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
5182 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
5183 #endif /* STM32F413xx || STM32F423xx */
5184 /**
5185  * @}
5186  */
5187 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
5188  * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
5189  * @note After reset, the peripheral clock (used for registers read/write access)
5190  * is disabled and the application software has to enable this clock before
5191  * using it.
5192  * @{
5193  */
5194 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
5195  __IO uint32_t tmpreg = 0x00U; \
5196  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
5197  /* Delay after an RCC peripheral clock enabling */ \
5198  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
5199  UNUSED(tmpreg); \
5200  } while(0U)
5201 #if defined(STM32F413xx) || defined(STM32F423xx)
5202 #define __HAL_RCC_UART9_CLK_ENABLE() do { \
5203  __IO uint32_t tmpreg = 0x00U; \
5204  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
5205  /* Delay after an RCC peripheral clock enabling */ \
5206  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
5207  UNUSED(tmpreg); \
5208  } while(0U)
5209 #define __HAL_RCC_UART10_CLK_ENABLE() do { \
5210  __IO uint32_t tmpreg = 0x00U; \
5211  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
5212  /* Delay after an RCC peripheral clock enabling */ \
5213  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
5214  UNUSED(tmpreg); \
5215  } while(0U)
5216 #endif /* STM32F413xx || STM32F423xx */
5217 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
5218  __IO uint32_t tmpreg = 0x00U; \
5219  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
5220  /* Delay after an RCC peripheral clock enabling */ \
5221  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
5222  UNUSED(tmpreg); \
5223  } while(0U)
5224 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
5225  __IO uint32_t tmpreg = 0x00U; \
5226  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
5227  /* Delay after an RCC peripheral clock enabling */ \
5228  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
5229  UNUSED(tmpreg); \
5230  } while(0U)
5231 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
5232  __IO uint32_t tmpreg = 0x00U; \
5233  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
5234  /* Delay after an RCC peripheral clock enabling */ \
5235  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
5236  UNUSED(tmpreg); \
5237  } while(0U)
5238 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
5239  __IO uint32_t tmpreg = 0x00U; \
5240  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
5241  /* Delay after an RCC peripheral clock enabling */ \
5242  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
5243  UNUSED(tmpreg); \
5244  } while(0U)
5245 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
5246  __IO uint32_t tmpreg = 0x00U; \
5247  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
5248  /* Delay after an RCC peripheral clock enabling */ \
5249  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
5250  UNUSED(tmpreg); \
5251  } while(0U)
5252 #if defined(STM32F413xx) || defined(STM32F423xx)
5253 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
5254  __IO uint32_t tmpreg = 0x00U; \
5255  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
5256  /* Delay after an RCC peripheral clock enabling */ \
5257  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
5258  UNUSED(tmpreg); \
5259  } while(0U)
5260 #endif /* STM32F413xx || STM32F423xx */
5261 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
5262  __IO uint32_t tmpreg = 0x00U; \
5263  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
5264  /* Delay after an RCC peripheral clock enabling */ \
5265  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
5266  UNUSED(tmpreg); \
5267  } while(0U)
5268 #if defined(STM32F413xx) || defined(STM32F423xx)
5269 #define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
5270  __IO uint32_t tmpreg = 0x00U; \
5271  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
5272  /* Delay after an RCC peripheral clock enabling */ \
5273  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
5274  UNUSED(tmpreg); \
5275  } while(0U)
5276 #endif /* STM32F413xx || STM32F423xx */
5277 
5278 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
5279 #if defined(STM32F413xx) || defined(STM32F423xx)
5280 #define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
5281 #define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))
5282 #endif /* STM32F413xx || STM32F423xx */
5283 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
5284 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
5285 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
5286 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
5287 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
5288 #if defined(STM32F413xx) || defined(STM32F423xx)
5289 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
5290 #endif /* STM32F413xx || STM32F423xx */
5291 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
5292 #if defined(STM32F413xx) || defined(STM32F423xx)
5293 #define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))
5294 #endif /* STM32F413xx || STM32F423xx */
5295 /**
5296  * @}
5297  */
5298 
5299 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
5300  * @brief Get the enable or disable status of the APB2 peripheral clock.
5301  * @note After reset, the peripheral clock (used for registers read/write access)
5302  * is disabled and the application software has to enable this clock before
5303  * using it.
5304  * @{
5305  */
5306 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
5307 #if defined(STM32F413xx) || defined(STM32F423xx)
5308 #define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
5309 #define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)
5310 #endif /* STM32F413xx || STM32F423xx */
5311 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
5312 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
5313 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
5314 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
5315 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
5316 #if defined(STM32F413xx) || defined(STM32F423xx)
5317 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
5318 #endif /* STM32F413xx || STM32F423xx */
5319 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
5320 #if defined(STM32F413xx) || defined(STM32F423xx)
5321 #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)
5322 #endif /* STM32F413xx || STM32F423xx */
5323 
5324 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
5325 #if defined(STM32F413xx) || defined(STM32F423xx)
5326 #define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET)
5327 #define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)
5328 #endif /* STM32F413xx || STM32F423xx */
5329 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
5330 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
5331 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
5332 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
5333 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
5334 #if defined(STM32F413xx) || defined(STM32F423xx)
5335 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
5336 #endif /* STM32F413xx || STM32F423xx */
5337 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
5338 #if defined(STM32F413xx) || defined(STM32F423xx)
5339 #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)
5340 #endif /* STM32F413xx || STM32F423xx */
5341 /**
5342  * @}
5343  */
5344 
5345 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
5346  * @brief Force or release AHB1 peripheral reset.
5347  * @{
5348  */
5349 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
5350 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
5351 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
5352 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
5353 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
5354 
5355 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
5356 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
5357 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
5358 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
5359 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
5360 /**
5361  * @}
5362  */
5363 
5364 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
5365  * @brief Force or release AHB2 peripheral reset.
5366  * @{
5367  */
5368 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
5369 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
5370 
5371 #if defined(STM32F423xx)
5372 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))
5373 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
5374 #endif /* STM32F423xx */
5375 
5376 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
5377 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
5378 
5379 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
5380 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
5381 /**
5382  * @}
5383  */
5384 
5385 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
5386  * @brief Force or release AHB3 peripheral reset.
5387  * @{
5388  */
5389 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5390 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
5391 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
5392 
5393 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
5394 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
5395 
5396 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
5397 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
5398 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5399 #if defined(STM32F412Cx)
5400 #define __HAL_RCC_AHB3_FORCE_RESET()
5401 #define __HAL_RCC_AHB3_RELEASE_RESET()
5402 
5403 #define __HAL_RCC_FSMC_FORCE_RESET()
5404 #define __HAL_RCC_QSPI_FORCE_RESET()
5405 
5406 #define __HAL_RCC_FSMC_RELEASE_RESET()
5407 #define __HAL_RCC_QSPI_RELEASE_RESET()
5408 #endif /* STM32F412Cx */
5409 /**
5410  * @}
5411  */
5412 
5413 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
5414  * @brief Force or release APB1 peripheral reset.
5415  * @{
5416  */
5417 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
5418 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
5419 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
5420 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
5421 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
5422 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
5423 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
5424 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
5425 #if defined(STM32F413xx) || defined(STM32F423xx)
5426 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
5427 #endif /* STM32F413xx || STM32F423xx */
5428 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
5429 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5430 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
5431 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5432 #if defined(STM32F413xx) || defined(STM32F423xx)
5433 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
5434 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
5435 #endif /* STM32F413xx || STM32F423xx */
5436 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
5437 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
5438 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
5439 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
5440 #if defined(STM32F413xx) || defined(STM32F423xx)
5441 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
5442 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
5443 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
5444 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
5445 #endif /* STM32F413xx || STM32F423xx */
5446 
5447 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
5448 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
5449 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
5450 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
5451 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
5452 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
5453 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
5454 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
5455 #if defined(STM32F413xx) || defined(STM32F423xx)
5456 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
5457 #endif /* STM32F413xx || STM32F423xx */
5458 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
5459 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5460 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
5461 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5462 #if defined(STM32F413xx) || defined(STM32F423xx)
5463 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
5464 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
5465 #endif /* STM32F413xx || STM32F423xx */
5466 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
5467 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
5468 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
5469 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
5470 #if defined(STM32F413xx) || defined(STM32F423xx)
5471 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
5472 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
5473 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
5474 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
5475 #endif /* STM32F413xx || STM32F423xx */
5476 /**
5477  * @}
5478  */
5479 
5480 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
5481  * @brief Force or release APB2 peripheral reset.
5482  * @{
5483  */
5484 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
5485 #if defined(STM32F413xx) || defined(STM32F423xx)
5486 #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST))
5487 #define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST))
5488 #endif /* STM32F413xx || STM32F423xx */
5489 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
5490 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
5491 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
5492 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
5493 #if defined(STM32F413xx) || defined(STM32F423xx)
5494 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
5495 #endif /* STM32F413xx || STM32F423xx */
5496 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
5497 #if defined(STM32F413xx) || defined(STM32F423xx)
5498 #define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST))
5499 #endif /* STM32F413xx || STM32F423xx */
5500 
5501 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
5502 #if defined(STM32F413xx) || defined(STM32F423xx)
5503 #define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
5504 #define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))
5505 #endif /* STM32F413xx || STM32F423xx */
5506 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
5507 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
5508 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
5509 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
5510 #if defined(STM32F413xx) || defined(STM32F423xx)
5511 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
5512 #endif /* STM32F413xx || STM32F423xx */
5513 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
5514 #if defined(STM32F413xx) || defined(STM32F423xx)
5515 #define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
5516 #endif /* STM32F413xx || STM32F423xx */
5517 /**
5518  * @}
5519  */
5520 
5521 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
5522  * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
5523  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
5524  * power consumption.
5525  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
5526  * @note By default, all peripheral clocks are enabled during SLEEP mode.
5527  * @{
5528  */
5529 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
5530 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
5531 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
5532 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
5533 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
5534 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
5535 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
5536 #if defined(STM32F413xx) || defined(STM32F423xx)
5537 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
5538 #endif /* STM32F413xx || STM32F423xx */
5539 
5540 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
5541 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
5542 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
5543 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
5544 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
5545 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
5546 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
5547 #if defined(STM32F413xx) || defined(STM32F423xx)
5548 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
5549 #endif /* STM32F413xx || STM32F423xx */
5550 /**
5551  * @}
5552  */
5553 
5554 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
5555  * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
5556  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
5557  * power consumption.
5558  * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
5559  * @note By default, all peripheral clocks are enabled during SLEEP mode.
5560  * @{
5561  */
5562 #if defined(STM32F423xx)
5563 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))
5564 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
5565 #endif /* STM32F423xx */
5566 
5567 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
5568 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
5569 
5570 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
5571 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
5572 /**
5573  * @}
5574  */
5575 
5576 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
5577  * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
5578  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
5579  * power consumption.
5580  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
5581  * @note By default, all peripheral clocks are enabled during SLEEP mode.
5582  * @{
5583  */
5584 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5585 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
5586 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
5587 
5588 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
5589 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
5590 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5591 
5592 /**
5593  * @}
5594  */
5595 
5596 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
5597  * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
5598  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
5599  * power consumption.
5600  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
5601  * @note By default, all peripheral clocks are enabled during SLEEP mode.
5602  * @{
5603  */
5604 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
5605 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
5606 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
5607 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
5608 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
5609 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
5610 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
5611 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
5612 #if defined(STM32F413xx) || defined(STM32F423xx)
5613 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
5614 #endif /* STM32F413xx || STM32F423xx */
5615 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
5616 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
5617 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5618 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
5619 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5620 #if defined(STM32F413xx) || defined(STM32F423xx)
5621 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
5622 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
5623 #endif /* STM32F413xx || STM32F423xx */
5624 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
5625 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
5626 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
5627 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
5628 #if defined(STM32F413xx) || defined(STM32F423xx)
5629 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
5630 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
5631 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
5632 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
5633 #endif /* STM32F413xx || STM32F423xx */
5634 
5635 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
5636 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
5637 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
5638 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
5639 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
5640 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
5641 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
5642 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
5643 #if defined(STM32F413xx) || defined(STM32F423xx)
5644 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
5645 #endif /* STM32F413xx || STM32F423xx */
5646 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
5647 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
5648 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5649 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
5650 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5651 #if defined(STM32F413xx) || defined(STM32F423xx)
5652 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
5653 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
5654 #endif /* STM32F413xx || STM32F423xx */
5655 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
5656 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
5657 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
5658 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
5659 #if defined(STM32F413xx) || defined(STM32F423xx)
5660 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
5661 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
5662 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
5663 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
5664 #endif /* STM32F413xx || STM32F423xx */
5665 /**
5666  * @}
5667  */
5668 
5669 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
5670  * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
5671  * @note Peripheral clock gating in SLEEP mode can be used to further reduce
5672  * power consumption.
5673  * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
5674  * @note By default, all peripheral clocks are enabled during SLEEP mode.
5675  * @{
5676  */
5677 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
5678 #if defined(STM32F413xx) || defined(STM32F423xx)
5679 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN))
5680 #define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN))
5681 #endif /* STM32F413xx || STM32F423xx */
5682 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
5683 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
5684 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
5685 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
5686 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
5687 #if defined(STM32F413xx) || defined(STM32F423xx)
5688 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
5689 #endif /* STM32F413xx || STM32F423xx */
5690 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
5691 #if defined(STM32F413xx) || defined(STM32F423xx)
5692 #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN))
5693 #endif /* STM32F413xx || STM32F423xx */
5694 
5695 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
5696 #if defined(STM32F413xx) || defined(STM32F423xx)
5697 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
5698 #define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))
5699 #endif /* STM32F413xx || STM32F423xx */
5700 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
5701 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
5702 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
5703 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
5704 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
5705 #if defined(STM32F413xx) || defined(STM32F423xx)
5706 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
5707 #endif /* STM32F413xx || STM32F423xx */
5708 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
5709 #if defined(STM32F413xx) || defined(STM32F423xx)
5710 #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
5711 #endif /* STM32F413xx || STM32F423xx */
5712 /**
5713  * @}
5714  */
5715 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
5716 /*----------------------------------------------------------------------------*/
5717 
5718 /*------------------------------- PLL Configuration --------------------------*/
5719 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
5720  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
5721  defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
5722 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
5723  * @note This function must be used only when the main PLL is disabled.
5724  * @param __RCC_PLLSource__ specifies the PLL entry clock source.
5725  * This parameter can be one of the following values:
5726  * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
5727  * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
5728  * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
5729  * @param __PLLM__ specifies the division factor for PLL VCO input clock
5730  * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
5731  * @note You have to set the PLLM parameter correctly to ensure that the VCO input
5732  * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
5733  * of 2 MHz to limit PLL jitter.
5734  * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
5735  * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
5736  * @note You have to set the PLLN parameter correctly to ensure that the VCO
5737  * output frequency is between 100 and 432 MHz.
5738  *
5739  * @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
5740  * This parameter must be a number in the range {2, 4, 6, or 8}.
5741  *
5742  * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
5743  * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
5744  * @note If the USB OTG FS is used in your application, you have to set the
5745  * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
5746  * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
5747  * correctly.
5748  *
5749  * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
5750  * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
5751  * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
5752  STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
5753  *
5754  */
5755 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
5756  (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
5757  ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
5758  ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \
5759  ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \
5760  ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
5761 #else
5762 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
5763  * @note This function must be used only when the main PLL is disabled.
5764  * @param __RCC_PLLSource__ specifies the PLL entry clock source.
5765  * This parameter can be one of the following values:
5766  * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
5767  * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
5768  * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
5769  * @param __PLLM__ specifies the division factor for PLL VCO input clock
5770  * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
5771  * @note You have to set the PLLM parameter correctly to ensure that the VCO input
5772  * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
5773  * of 2 MHz to limit PLL jitter.
5774  * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
5775  * This parameter must be a number between Min_Data = 50 and Max_Data = 432
5776  * Except for STM32F411xE devices where Min_Data = 192.
5777  * @note You have to set the PLLN parameter correctly to ensure that the VCO
5778  * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
5779  * where frequency is between 192 and 432 MHz.
5780  * @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
5781  * This parameter must be a number in the range {2, 4, 6, or 8}.
5782  *
5783  * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
5784  * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
5785  * @note If the USB OTG FS is used in your application, you have to set the
5786  * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
5787  * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
5788  * correctly.
5789  *
5790  */
5791 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
5792  (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
5793  ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
5794  ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \
5795  ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
5796  #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
5797 /*----------------------------------------------------------------------------*/
5798 
5799 /*----------------------------PLLI2S Configuration ---------------------------*/
5800 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
5801  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
5802  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
5803  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
5804  defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
5805 
5806 /** @brief Macros to enable or disable the PLLI2S.
5807  * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
5808  */
5809 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
5810 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
5811 
5812 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
5813  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
5814  STM32F412Rx || STM32F412Cx */
5815 #if defined(STM32F446xx)
5816 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
5817  * @note This macro must be used only when the PLLI2S is disabled.
5818  * @note PLLI2S clock source is common with the main PLL (configured in
5819  * HAL_RCC_ClockConfig() API).
5820  * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
5821  * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
5822  * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
5823  * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
5824  * of 1 MHz to limit PLLI2S jitter.
5825  *
5826  * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
5827  * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
5828  * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
5829  * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
5830  *
5831  * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock.
5832  * This parameter must be a number in the range {2, 4, 6, or 8}.
5833  * @note the PLLI2SP parameter is only available with STM32F446xx Devices
5834  *
5835  * @param __PLLI2SR__ specifies the division factor for I2S clock
5836  * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
5837  * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
5838  * on the I2S clock frequency.
5839  *
5840  * @param __PLLI2SQ__ specifies the division factor for SAI clock
5841  * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
5842  */
5843 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
5844  (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
5845  ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
5846  ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\
5847  ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
5848  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
5849 #elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
5850  defined(STM32F413xx) || defined(STM32F423xx)
5851 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
5852  * @note This macro must be used only when the PLLI2S is disabled.
5853  * @note PLLI2S clock source is common with the main PLL (configured in
5854  * HAL_RCC_ClockConfig() API).
5855  * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
5856  * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
5857  * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
5858  * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
5859  * of 1 MHz to limit PLLI2S jitter.
5860  *
5861  * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
5862  * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
5863  * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
5864  * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
5865  *
5866  * @param __PLLI2SR__ specifies the division factor for I2S clock
5867  * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
5868  * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
5869  * on the I2S clock frequency.
5870  *
5871  * @param __PLLI2SQ__ specifies the division factor for SAI clock
5872  * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
5873  */
5874 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
5875  (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
5876  ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
5877  ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
5878  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
5879 #else
5880 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
5881  * @note This macro must be used only when the PLLI2S is disabled.
5882  * @note PLLI2S clock source is common with the main PLL (configured in
5883  * HAL_RCC_ClockConfig() API).
5884  * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
5885  * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
5886  * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
5887  * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
5888  *
5889  * @param __PLLI2SR__ specifies the division factor for I2S clock
5890  * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
5891  * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
5892  * on the I2S clock frequency.
5893  *
5894  */
5895 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
5896  (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
5897  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
5898 #endif /* STM32F446xx */
5899 
5900 #if defined(STM32F411xE)
5901 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
5902  * @note This macro must be used only when the PLLI2S is disabled.
5903  * @note This macro must be used only when the PLLI2S is disabled.
5904  * @note PLLI2S clock source is common with the main PLL (configured in
5905  * HAL_RCC_ClockConfig() API).
5906  * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
5907  * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
5908  * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
5909  * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
5910  * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
5911  * of 2 MHz to limit PLLI2S jitter.
5912  * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
5913  * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
5914  * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
5915  * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
5916  * @param __PLLI2SR__ specifies the division factor for I2S clock
5917  * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
5918  * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
5919  * on the I2S clock frequency.
5920  */
5921 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
5922  ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
5923  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
5924 #endif /* STM32F411xE */
5925 
5926 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
5927 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
5928  * @note This macro must be used only when the PLLI2S is disabled.
5929  * @note PLLI2S clock source is common with the main PLL (configured in
5930  * HAL_RCC_ClockConfig() API)
5931  * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
5932  * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
5933  * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
5934  * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
5935  * @param __PLLI2SQ__ specifies the division factor for SAI1 clock.
5936  * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
5937  * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
5938  * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
5939  * @param __PLLI2SR__ specifies the division factor for I2S clock
5940  * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
5941  * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
5942  * on the I2S clock frequency.
5943  */
5944 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\
5945  ((__PLLI2SQ__) << 24U) |\
5946  ((__PLLI2SR__) << 28U))
5947 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
5948 /*----------------------------------------------------------------------------*/
5949 
5950 /*------------------------------ PLLSAI Configuration ------------------------*/
5951 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
5952 /** @brief Macros to Enable or Disable the PLLISAI.
5953  * @note The PLLSAI is only available with STM32F429x/439x Devices.
5954  * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
5955  */
5956 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
5957 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
5958 
5959 #if defined(STM32F446xx)
5960 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
5961  *
5962  * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock
5963  * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
5964  * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
5965  * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
5966  * of 1 MHz to limit PLLI2S jitter.
5967  * @note The PLLSAIM parameter is only used with STM32F446xx Devices
5968  *
5969  * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
5970  * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
5971  * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
5972  * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
5973  *
5974  * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks.
5975  * This parameter must be a number in the range {2, 4, 6, or 8}.
5976  * @note the PLLSAIP parameter is only available with STM32F446xx Devices
5977  *
5978  * @param __PLLSAIQ__ specifies the division factor for SAI clock
5979  * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
5980  *
5981  * @param __PLLSAIR__ specifies the division factor for LTDC clock
5982  * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
5983  * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
5984  */
5985 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
5986  (RCC->PLLSAICFGR = ((__PLLSAIM__) | \
5987  ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \
5988  ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \
5989  ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)))
5990 #endif /* STM32F446xx */
5991 
5992 #if defined(STM32F469xx) || defined(STM32F479xx)
5993 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
5994  *
5995  * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
5996  * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
5997  * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
5998  * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
5999  *
6000  * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks.
6001  * This parameter must be a number in the range {2, 4, 6, or 8}.
6002  *
6003  * @param __PLLSAIQ__ specifies the division factor for SAI clock
6004  * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
6005  *
6006  * @param __PLLSAIR__ specifies the division factor for LTDC clock
6007  * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
6008  */
6009 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
6010  (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\
6011  ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\
6012  ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\
6013  ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
6014 #endif /* STM32F469xx || STM32F479xx */
6015 
6016 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
6017 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
6018  *
6019  * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
6020  * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
6021  * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
6022  * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
6023  *
6024  * @param __PLLSAIQ__ specifies the division factor for SAI clock
6025  * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
6026  *
6027  * @param __PLLSAIR__ specifies the division factor for LTDC clock
6028  * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
6029  * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
6030  */
6031 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
6032  (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \
6033  ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \
6034  ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
6035 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
6036 
6037 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6038 /*----------------------------------------------------------------------------*/
6039 
6040 /*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/
6041 #if defined(STM32F413xx) || defined(STM32F423xx)
6042 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
6043  * @note This function must be called before enabling the PLLI2S.
6044  * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock.
6045  * This parameter must be a number between 1 and 32.
6046  * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__
6047  */
6048 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
6049 
6050 /** @brief Macro to configure the SAI clock Divider coming from PLL.
6051  * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock.
6052  * This parameter must be a number between 1 and 32.
6053  * SAI1 clock frequency = f(PLLR) / __PLLDivR__
6054  */
6055 #define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))
6056 #endif /* STM32F413xx || STM32F423xx */
6057 
6058 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
6059  defined(STM32F469xx) || defined(STM32F479xx)
6060 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
6061  * @note This function must be called before enabling the PLLI2S.
6062  * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock.
6063  * This parameter must be a number between 1 and 32.
6064  * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
6065  */
6066 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
6067 
6068 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
6069  * @note This function must be called before enabling the PLLSAI.
6070  * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .
6071  * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
6072  * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
6073  */
6074 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
6075 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6076 
6077 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
6078 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
6079  *
6080  * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
6081  * @note This function must be called before enabling the PLLSAI.
6082  * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
6083  * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
6084  * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
6085  */
6086 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
6087 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
6088 /*----------------------------------------------------------------------------*/
6089 
6090 /*------------------------- Peripheral Clock selection -----------------------*/
6091 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
6092  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
6093  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
6094  defined(STM32F479xx)
6095 /** @brief Macro to configure the I2S clock source (I2SCLK).
6096  * @note This function must be called before enabling the I2S APB clock.
6097  * @param __SOURCE__ specifies the I2S clock source.
6098  * This parameter can be one of the following values:
6099  * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
6100  * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
6101  * used as I2S clock source.
6102  */
6103 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
6104 
6105 
6106 /** @brief Macro to get the I2S clock source (I2SCLK).
6107  * @retval The clock source can be one of the following values:
6108  * @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
6109  * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
6110  * used as I2S clock source
6111  */
6112 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
6113 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
6114 
6115 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
6116 
6117 /** @brief Macro to configure SAI1BlockA clock source selection.
6118  * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
6119  * @note This function must be called before enabling PLLSAI, PLLI2S and
6120  * the SAI clock.
6121  * @param __SOURCE__ specifies the SAI Block A clock source.
6122  * This parameter can be one of the following values:
6123  * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
6124  * as SAI1 Block A clock.
6125  * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
6126  * as SAI1 Block A clock.
6127  * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
6128  * used as SAI1 Block A clock.
6129  */
6130 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
6131 
6132 /** @brief Macro to configure SAI1BlockB clock source selection.
6133  * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
6134  * @note This function must be called before enabling PLLSAI, PLLI2S and
6135  * the SAI clock.
6136  * @param __SOURCE__ specifies the SAI Block B clock source.
6137  * This parameter can be one of the following values:
6138  * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
6139  * as SAI1 Block B clock.
6140  * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
6141  * as SAI1 Block B clock.
6142  * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
6143  * used as SAI1 Block B clock.
6144  */
6145 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
6146 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
6147 
6148 #if defined(STM32F446xx)
6149 /** @brief Macro to configure SAI1 clock source selection.
6150  * @note This configuration is only available with STM32F446xx Devices.
6151  * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
6152  * the SAI clock.
6153  * @param __SOURCE__ specifies the SAI1 clock source.
6154  * This parameter can be one of the following values:
6155  * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
6156  * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
6157  * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
6158  * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
6159  */
6160 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
6161 
6162 /** @brief Macro to Get SAI1 clock source selection.
6163  * @note This configuration is only available with STM32F446xx Devices.
6164  * @retval The clock source can be one of the following values:
6165  * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
6166  * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
6167  * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
6168  * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
6169  */
6170 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
6171 
6172 /** @brief Macro to configure SAI2 clock source selection.
6173  * @note This configuration is only available with STM32F446xx Devices.
6174  * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
6175  * the SAI clock.
6176  * @param __SOURCE__ specifies the SAI2 clock source.
6177  * This parameter can be one of the following values:
6178  * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
6179  * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
6180  * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
6181  * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
6182  */
6183 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
6184 
6185 /** @brief Macro to Get SAI2 clock source selection.
6186  * @note This configuration is only available with STM32F446xx Devices.
6187  * @retval The clock source can be one of the following values:
6188  * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
6189  * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
6190  * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
6191  * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
6192  */
6193 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
6194 
6195 /** @brief Macro to configure I2S APB1 clock source selection.
6196  * @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
6197  * @param __SOURCE__ specifies the I2S APB1 clock source.
6198  * This parameter can be one of the following values:
6199  * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
6200  * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
6201  * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
6202  * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6203  */
6204 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
6205 
6206 /** @brief Macro to Get I2S APB1 clock source selection.
6207  * @retval The clock source can be one of the following values:
6208  * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
6209  * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
6210  * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
6211  * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6212  */
6213 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
6214 
6215 /** @brief Macro to configure I2S APB2 clock source selection.
6216  * @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
6217  * @param __SOURCE__ specifies the SAI Block A clock source.
6218  * This parameter can be one of the following values:
6219  * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
6220  * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
6221  * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
6222  * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6223  */
6224 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
6225 
6226 /** @brief Macro to Get I2S APB2 clock source selection.
6227  * @retval The clock source can be one of the following values:
6228  * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
6229  * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
6230  * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
6231  * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6232  */
6233 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
6234 
6235 /** @brief Macro to configure the CEC clock.
6236  * @param __SOURCE__ specifies the CEC clock source.
6237  * This parameter can be one of the following values:
6238  * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
6239  * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
6240  */
6241 #define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
6242 
6243 /** @brief Macro to Get the CEC clock.
6244  * @retval The clock source can be one of the following values:
6245  * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
6246  * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
6247  */
6248 #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
6249 
6250 /** @brief Macro to configure the FMPI2C1 clock.
6251  * @param __SOURCE__ specifies the FMPI2C1 clock source.
6252  * This parameter can be one of the following values:
6253  * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
6254  * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
6255  * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
6256  */
6257 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
6258 
6259 /** @brief Macro to Get the FMPI2C1 clock.
6260  * @retval The clock source can be one of the following values:
6261  * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
6262  * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
6263  * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
6264  */
6265 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
6266 
6267 /** @brief Macro to configure the CLK48 clock.
6268  * @param __SOURCE__ specifies the CLK48 clock source.
6269  * This parameter can be one of the following values:
6270  * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
6271  * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
6272  */
6273 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
6274 
6275 /** @brief Macro to Get the CLK48 clock.
6276  * @retval The clock source can be one of the following values:
6277  * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
6278  * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
6279  */
6280 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
6281 
6282 /** @brief Macro to configure the SDIO clock.
6283  * @param __SOURCE__ specifies the SDIO clock source.
6284  * This parameter can be one of the following values:
6285  * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
6286  * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
6287  */
6288 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
6289 
6290 /** @brief Macro to Get the SDIO clock.
6291  * @retval The clock source can be one of the following values:
6292  * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
6293  * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
6294  */
6295 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
6296 
6297 /** @brief Macro to configure the SPDIFRX clock.
6298  * @param __SOURCE__ specifies the SPDIFRX clock source.
6299  * This parameter can be one of the following values:
6300  * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
6301  * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
6302  */
6303 #define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
6304 
6305 /** @brief Macro to Get the SPDIFRX clock.
6306  * @retval The clock source can be one of the following values:
6307  * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
6308  * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
6309  */
6310 #define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
6311 #endif /* STM32F446xx */
6312 
6313 #if defined(STM32F469xx) || defined(STM32F479xx)
6314 
6315 /** @brief Macro to configure the CLK48 clock.
6316  * @param __SOURCE__ specifies the CLK48 clock source.
6317  * This parameter can be one of the following values:
6318  * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
6319  * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
6320  */
6321 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
6322 
6323 /** @brief Macro to Get the CLK48 clock.
6324  * @retval The clock source can be one of the following values:
6325  * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
6326  * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
6327  */
6328 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
6329 
6330 /** @brief Macro to configure the SDIO clock.
6331  * @param __SOURCE__ specifies the SDIO clock source.
6332  * This parameter can be one of the following values:
6333  * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
6334  * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
6335  */
6336 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
6337 
6338 /** @brief Macro to Get the SDIO clock.
6339  * @retval The clock source can be one of the following values:
6340  * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
6341  * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
6342  */
6343 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
6344 
6345 /** @brief Macro to configure the DSI clock.
6346  * @param __SOURCE__ specifies the DSI clock source.
6347  * This parameter can be one of the following values:
6348  * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
6349  * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
6350  */
6351 #define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
6352 
6353 /** @brief Macro to Get the DSI clock.
6354  * @retval The clock source can be one of the following values:
6355  * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
6356  * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
6357  */
6358 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
6359 
6360 #endif /* STM32F469xx || STM32F479xx */
6361 
6362 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
6363  defined(STM32F413xx) || defined(STM32F423xx)
6364  /** @brief Macro to configure the DFSDM1 clock.
6365  * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
6366  * This parameter can be one of the following values:
6367  * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
6368  * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
6369  * @retval None
6370  */
6371 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
6372 
6373 /** @brief Macro to get the DFSDM1 clock source.
6374  * @retval The clock source can be one of the following values:
6375  * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
6376  * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
6377  */
6378 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
6379 
6380 /** @brief Macro to configure DFSDM1 Audio clock source selection.
6381  * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
6382  STM32F413xx/STM32F423xx Devices.
6383  * @param __SOURCE__ specifies the DFSDM1 Audio clock source.
6384  * This parameter can be one of the following values:
6385  * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
6386  * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
6387  */
6388 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
6389 
6390 /** @brief Macro to Get DFSDM1 Audio clock source selection.
6391  * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
6392  STM32F413xx/STM32F423xx Devices.
6393  * @retval The clock source can be one of the following values:
6394  * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
6395  * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
6396  */
6397 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
6398 
6399 #if defined(STM32F413xx) || defined(STM32F423xx)
6400  /** @brief Macro to configure the DFSDM2 clock.
6401  * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
6402  * This parameter can be one of the following values:
6403  * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
6404  * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
6405  * @retval None
6406  */
6407 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
6408 
6409 /** @brief Macro to get the DFSDM2 clock source.
6410  * @retval The clock source can be one of the following values:
6411  * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
6412  * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
6413  */
6414 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
6415 
6416 /** @brief Macro to configure DFSDM1 Audio clock source selection.
6417  * @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
6418  * @param __SOURCE__ specifies the DFSDM2 Audio clock source.
6419  * This parameter can be one of the following values:
6420  * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
6421  * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
6422  */
6423 #define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
6424 
6425 /** @brief Macro to Get DFSDM2 Audio clock source selection.
6426  * @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
6427  * @retval The clock source can be one of the following values:
6428  * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
6429  * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
6430  */
6431 #define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
6432 
6433 /** @brief Macro to configure SAI1BlockA clock source selection.
6434  * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
6435  * @note This function must be called before enabling PLLSAI, PLLI2S and
6436  * the SAI clock.
6437  * @param __SOURCE__ specifies the SAI Block A clock source.
6438  * This parameter can be one of the following values:
6439  * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
6440  * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
6441  * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
6442  * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6443  */
6444 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
6445 
6446 /** @brief Macro to Get SAI1 BlockA clock source selection.
6447  * @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
6448  * @retval The clock source can be one of the following values:
6449  * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
6450  * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
6451  * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
6452  * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6453  */
6454 #define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
6455 
6456 /** @brief Macro to configure SAI1 BlockB clock source selection.
6457  * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
6458  * @note This function must be called before enabling PLLSAI, PLLI2S and
6459  * the SAI clock.
6460  * @param __SOURCE__ specifies the SAI Block B clock source.
6461  * This parameter can be one of the following values:
6462  * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
6463  * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
6464  * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
6465  * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6466  */
6467 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
6468 
6469 /** @brief Macro to Get SAI1 BlockB clock source selection.
6470  * @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
6471  * @retval The clock source can be one of the following values:
6472  * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
6473  * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
6474  * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
6475  * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6476  */
6477 #define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
6478 
6479 /** @brief Macro to configure the LPTIM1 clock.
6480  * @param __SOURCE__ specifies the LPTIM1 clock source.
6481  * This parameter can be one of the following values:
6482  * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
6483  * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
6484  * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
6485  * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
6486  */
6487 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
6488 
6489 /** @brief Macro to Get the LPTIM1 clock.
6490  * @retval The clock source can be one of the following values:
6491  * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
6492  * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
6493  * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
6494  * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
6495  */
6496 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
6497 #endif /* STM32F413xx || STM32F423xx */
6498 
6499 /** @brief Macro to configure I2S APB1 clock source selection.
6500  * @param __SOURCE__ specifies the I2S APB1 clock source.
6501  * This parameter can be one of the following values:
6502  * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
6503  * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
6504  * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
6505  * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6506  */
6507 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
6508 
6509 /** @brief Macro to Get I2S APB1 clock source selection.
6510  * @retval The clock source can be one of the following values:
6511  * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
6512  * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
6513  * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
6514  * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6515  */
6516 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
6517 
6518 /** @brief Macro to configure I2S APB2 clock source selection.
6519  * @param __SOURCE__ specifies the I2S APB2 clock source.
6520  * This parameter can be one of the following values:
6521  * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
6522  * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
6523  * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
6524  * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6525  */
6526 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
6527 
6528 /** @brief Macro to Get I2S APB2 clock source selection.
6529  * @retval The clock source can be one of the following values:
6530  * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
6531  * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
6532  * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
6533  * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6534  */
6535 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
6536 
6537 /** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK).
6538  * @note This macro must be called before enabling the I2S APB clock.
6539  * @param __SOURCE__ specifies the I2S clock source.
6540  * This parameter can be one of the following values:
6541  * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
6542  * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
6543  * used as I2S clock source.
6544  */
6545 #define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
6546 
6547 /** @brief Macro to configure the FMPI2C1 clock.
6548  * @param __SOURCE__ specifies the FMPI2C1 clock source.
6549  * This parameter can be one of the following values:
6550  * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
6551  * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
6552  * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
6553  */
6554 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
6555 
6556 /** @brief Macro to Get the FMPI2C1 clock.
6557  * @retval The clock source can be one of the following values:
6558  * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
6559  * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
6560  * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
6561  */
6562 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
6563 
6564 /** @brief Macro to configure the CLK48 clock.
6565  * @param __SOURCE__ specifies the CLK48 clock source.
6566  * This parameter can be one of the following values:
6567  * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
6568  * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
6569  */
6570 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
6571 
6572 /** @brief Macro to Get the CLK48 clock.
6573  * @retval The clock source can be one of the following values:
6574  * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
6575  * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
6576  */
6577 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
6578 
6579 /** @brief Macro to configure the SDIO clock.
6580  * @param __SOURCE__ specifies the SDIO clock source.
6581  * This parameter can be one of the following values:
6582  * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
6583  * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
6584  */
6585 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
6586 
6587 /** @brief Macro to Get the SDIO clock.
6588  * @retval The clock source can be one of the following values:
6589  * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
6590  * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
6591  */
6592 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
6593 
6594 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
6595 
6596 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6597 /** @brief Macro to configure I2S clock source selection.
6598  * @param __SOURCE__ specifies the I2S clock source.
6599  * This parameter can be one of the following values:
6600  * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
6601  * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
6602  * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
6603  */
6604 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
6605 
6606 /** @brief Macro to Get I2S clock source selection.
6607  * @retval The clock source can be one of the following values:
6608  * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
6609  * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
6610  * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
6611  */
6612 #define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
6613 
6614 /** @brief Macro to configure the FMPI2C1 clock.
6615  * @param __SOURCE__ specifies the FMPI2C1 clock source.
6616  * This parameter can be one of the following values:
6617  * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
6618  * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
6619  * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
6620  */
6621 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
6622 
6623 /** @brief Macro to Get the FMPI2C1 clock.
6624  * @retval The clock source can be one of the following values:
6625  * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
6626  * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
6627  * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
6628  */
6629 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
6630 
6631 /** @brief Macro to configure the LPTIM1 clock.
6632  * @param __SOURCE__ specifies the LPTIM1 clock source.
6633  * This parameter can be one of the following values:
6634  * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
6635  * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
6636  * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
6637  * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
6638  */
6639 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
6640 
6641 /** @brief Macro to Get the LPTIM1 clock.
6642  * @retval The clock source can be one of the following values:
6643  * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
6644  * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
6645  * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
6646  * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
6647  */
6648 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
6649 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6650 
6651 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
6652  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
6653  defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
6654  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
6655  defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
6656 /** @brief Macro to configure the Timers clocks prescalers
6657  * @note This feature is only available with STM32F429x/439x Devices.
6658  * @param __PRESC__ specifies the Timers clocks prescalers selection
6659  * This parameter can be one of the following values:
6660  * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
6661  * equal to HPRE if PPREx is corresponding to division by 1 or 2,
6662  * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
6663  * division by 4 or more.
6664  * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
6665  * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
6666  * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
6667  * to division by 8 or more.
6668  */
6669 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
6670 
6671 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\
6672  STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\
6673  STM32F423xx */
6674 
6675 /*----------------------------------------------------------------------------*/
6676 
6677 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
6678 /** @brief Enable PLLSAI_RDY interrupt.
6679  */
6680 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
6681 
6682 /** @brief Disable PLLSAI_RDY interrupt.
6683  */
6684 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
6685 
6686 /** @brief Clear the PLLSAI RDY interrupt pending bits.
6687  */
6688 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
6689 
6690 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
6691  * @retval The new state (TRUE or FALSE).
6692  */
6693 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
6694 
6695 /** @brief Check PLLSAI RDY flag is set or not.
6696  * @retval The new state (TRUE or FALSE).
6697  */
6698 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
6699 
6700 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6701 
6702 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6703 /** @brief Macros to enable or disable the RCC MCO1 feature.
6704  */
6705 #define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
6706 #define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
6707 
6708 /** @brief Macros to enable or disable the RCC MCO2 feature.
6709  */
6710 #define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
6711 #define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)
6712 
6713 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6714 
6715 /**
6716  * @}
6717  */
6718 
6719 /* Exported functions --------------------------------------------------------*/
6720 /** @addtogroup RCCEx_Exported_Functions
6721  * @{
6722  */
6723 
6724 /** @addtogroup RCCEx_Exported_Functions_Group1
6725  * @{
6726  */
6727 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
6728 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
6729 
6730 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
6731 
6732 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
6733  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
6734  defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
6735  defined(STM32F423xx)
6736 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
6737 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
6738 #if defined(RCC_PLLI2S_SUPPORT)
6739 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
6740 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
6741 #endif /* RCC_PLLI2S_SUPPORT */
6742 #if defined(RCC_PLLSAI_SUPPORT)
6743 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit);
6744 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
6745 #endif /* RCC_PLLSAI_SUPPORT */
6746 /**
6747  * @}
6748  */
6749 
6750 /**
6751  * @}
6752  */
6753 /* Private types -------------------------------------------------------------*/
6754 /* Private variables ---------------------------------------------------------*/
6755 /* Private constants ---------------------------------------------------------*/
6756 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
6757  * @{
6758  */
6759 
6760 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
6761  * @brief RCC registers bit address in the alias region
6762  * @{
6763  */
6764 /* --- CR Register ---*/
6765 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
6766  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
6767 /* Alias word address of PLLSAION bit */
6768 #define RCC_PLLSAION_BIT_NUMBER 0x1CU
6769 #define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
6770 
6771 #define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
6772 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6773 
6774 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
6775  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
6776  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
6777  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
6778  defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
6779 /* Alias word address of PLLI2SON bit */
6780 #define RCC_PLLI2SON_BIT_NUMBER 0x1AU
6781 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
6782 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
6783  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
6784  STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
6785 
6786 /* --- DCKCFGR Register ---*/
6787 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
6788  defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
6789  defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
6790  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
6791  defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
6792 /* Alias word address of TIMPRE bit */
6793 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU)
6794 #define RCC_TIMPRE_BIT_NUMBER 0x18U
6795 #define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
6796 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\
6797  STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
6798  STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
6799 
6800 /* --- CFGR Register ---*/
6801 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
6802 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
6803  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
6804  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
6805  defined(STM32F469xx) || defined(STM32F479xx)
6806 /* Alias word address of I2SSRC bit */
6807 #define RCC_I2SSRC_BIT_NUMBER 0x17U
6808 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
6809 
6810 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
6811 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
6812  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
6813 
6814 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
6815  defined(STM32F413xx) || defined(STM32F423xx)
6816 /* --- PLLI2SCFGR Register ---*/
6817 #define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
6818 /* Alias word address of PLLI2SSRC bit */
6819 #define RCC_PLLI2SSRC_BIT_NUMBER 0x16U
6820 #define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
6821 
6822 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
6823 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */
6824 
6825 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6826 /* Alias word address of MCO1EN bit */
6827 #define RCC_MCO1EN_BIT_NUMBER 0x8U
6828 #define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
6829 
6830 /* Alias word address of MCO2EN bit */
6831 #define RCC_MCO2EN_BIT_NUMBER 0x9U
6832 #define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
6833 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6834 
6835 #define PLL_TIMEOUT_VALUE 2U /* 2 ms */
6836 /**
6837  * @}
6838  */
6839 
6840 /**
6841  * @}
6842  */
6843 
6844 /* Private macros ------------------------------------------------------------*/
6845 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
6846  * @{
6847  */
6848 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
6849  * @{
6850  */
6851 #if defined(STM32F411xE)
6852 #define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
6853 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
6854 #else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||
6855  STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx ||
6856  STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Cx || STM32F412Rx ||
6857  STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
6858 #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
6859 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
6860 #endif /* STM32F411xE */
6861 
6862 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
6863 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
6864 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
6865 
6866 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
6867 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
6868 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
6869 
6870 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
6871 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
6872 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
6873 
6874 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6875 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
6876 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6877 
6878 #if defined(STM32F446xx)
6879 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
6880 #endif /* STM32F446xx */
6881 
6882 #if defined(STM32F469xx) || defined(STM32F479xx)
6883 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
6884 #endif /* STM32F469xx || STM32F479xx */
6885 
6886 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
6887 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
6888 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
6889 
6890 #if defined(STM32F413xx) || defined(STM32F423xx)
6891 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
6892 #endif /* STM32F413xx || STM32F423xx */
6893 
6894 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6895 
6896 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
6897  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
6898 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
6899 
6900 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
6901 
6902 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
6903 
6904 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6905 
6906 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
6907 
6908 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
6909 
6910 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
6911  ((VALUE) == RCC_PLLSAIDIVR_4) ||\
6912  ((VALUE) == RCC_PLLSAIDIVR_8) ||\
6913  ((VALUE) == RCC_PLLSAIDIVR_16))
6914 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6915 
6916 #if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
6917  defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
6918 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))
6919 
6920 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
6921  ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
6922 #endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
6923 
6924 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6925 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6926 
6927 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
6928  ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
6929 
6930 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\
6931  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
6932  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
6933 
6934 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
6935  ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
6936  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
6937  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
6938 
6939 #define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\
6940  ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\
6941  ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
6942 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6943 
6944 #if defined(STM32F446xx)
6945 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6946 
6947 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
6948  ((VALUE) == RCC_PLLI2SP_DIV4) ||\
6949  ((VALUE) == RCC_PLLI2SP_DIV6) ||\
6950  ((VALUE) == RCC_PLLI2SP_DIV8))
6951 
6952 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
6953 
6954 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
6955  ((VALUE) == RCC_PLLSAIP_DIV4) ||\
6956  ((VALUE) == RCC_PLLSAIP_DIV6) ||\
6957  ((VALUE) == RCC_PLLSAIP_DIV8))
6958 
6959 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
6960  ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
6961  ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\
6962  ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
6963 
6964 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
6965  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
6966  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\
6967  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
6968 
6969 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
6970  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\
6971  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\
6972  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
6973 
6974  #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
6975  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\
6976  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\
6977  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
6978 
6979 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\
6980  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
6981  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
6982 
6983 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\
6984  ((SOURCE) == RCC_CECCLKSOURCE_LSE))
6985 
6986 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
6987  ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
6988 
6989 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
6990  ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
6991 
6992 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
6993  ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
6994 #endif /* STM32F446xx */
6995 
6996 #if defined(STM32F469xx) || defined(STM32F479xx)
6997 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6998 
6999 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
7000  ((VALUE) == RCC_PLLSAIP_DIV4) ||\
7001  ((VALUE) == RCC_PLLSAIP_DIV6) ||\
7002  ((VALUE) == RCC_PLLSAIP_DIV8))
7003 
7004 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
7005  ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
7006 
7007 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
7008  ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
7009 
7010 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\
7011  ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
7012 
7013 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
7014  ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
7015 #endif /* STM32F469xx || STM32F479xx */
7016 
7017 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
7018  defined(STM32F413xx) || defined(STM32F423xx)
7019 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
7020 
7021 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
7022 
7023 #define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \
7024  ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
7025 
7026 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
7027  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\
7028  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\
7029  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
7030 
7031  #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
7032  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\
7033  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\
7034  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
7035 
7036 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\
7037  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
7038  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
7039 
7040 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
7041  ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
7042 
7043 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
7044  ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
7045 
7046 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
7047  ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
7048 
7049 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \
7050  ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
7051 
7052 #if defined(STM32F413xx) || defined(STM32F423xx)
7053 #define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \
7054  ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
7055 
7056 #define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \
7057  ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
7058 
7059 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
7060  ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
7061  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
7062  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
7063 
7064 #define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\
7065  ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\
7066  ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\
7067  ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
7068 
7069 #define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\
7070  ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\
7071  ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\
7072  ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
7073 
7074 #define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
7075 
7076 #define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
7077 
7078 #endif /* STM32F413xx || STM32F423xx */
7079 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
7080 
7081 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
7082  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
7083  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
7084  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
7085  defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
7086 
7087 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
7088  ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
7089 
7090 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
7091  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
7092  STM32F412Rx */
7093 
7094 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
7095 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
7096  ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
7097 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
7098 /**
7099  * @}
7100  */
7101 
7102 /**
7103  * @}
7104  */
7105 
7106 /**
7107  * @}
7108  */
7109 
7110 /**
7111  * @}
7112  */
7113 #ifdef __cplusplus
7114 }
7115 #endif
7116 
7117 #endif /* __STM32F4xx_HAL_RCC_EX_H */
7118 
7119 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
RCC_PLLInitTypeDef::PLLP
uint32_t PLLP
Definition: stm32f4xx_hal_rcc_ex.h:78
HAL_RCCEx_PeriphCLKConfig
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
HAL_RCCEx_GetPeriphCLKConfig
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
HAL_RCCEx_GetPeriphCLKFreq
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
RCC_PLLInitTypeDef::PLLQ
uint32_t PLLQ
Definition: stm32f4xx_hal_rcc_ex.h:81
RCC_PLLInitTypeDef::PLLSource
uint32_t PLLSource
Definition: stm32f4xx_hal_rcc_ex.h:68
RCC_PLLInitTypeDef::PLLM
uint32_t PLLM
Definition: stm32f4xx_hal_rcc_ex.h:71
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:55
RCC_PLLInitTypeDef::PLLState
uint32_t PLLState
Definition: stm32f4xx_hal_rcc_ex.h:65
uint8_t
const uint8_t[]
Definition: 404_html.c:3
RCC_PLLInitTypeDef::PLLN
uint32_t PLLN
Definition: stm32f4xx_hal_rcc_ex.h:74
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition: stm32f4xx_hal_rcc_ex.h:63